• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.204-207
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• 2003

The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet to tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of sample was conducted. A TiW/Cu UBM structure was adopted and sample was aging treated to analyze the effect of intermetallic compound with time variation. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the fine joint area was observed by using SEM, TEM and EDS. In result, the shear strength was decreased of about 20% in the $100{\mu}m$ sample at $170^{\circ}C$ aging compared with the maximum shear strength of same pad size sample. In the case of the $120^{\circ}C$ aging treatment, 17% of decrease in shear strength was measured at the $100{\mu}m$ pad size sample. Also, intremetallic compound of $Cu_6Sn_5$ and $Cu_3Sn$ were observed through the TEM measurement by using an FIB technique that is very useful to prepare TEM thin foil specimens from the solder joint interface.

• ETRI Journal
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• v.37 no.2
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• pp.387-394
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• 2015

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.700-708
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• 1996

Electroless plating technique was utilized to flip chip bonding to improve surface mount characteristics. Each step of plating procedure was studied in terms pf pH, plating temperature and plating time. Al patterned 4 inch Si wafers were used as substrstes and zincate was used as an activation solution. Heat treatment was carried out for all the specimens in the temperature range from room temperature to $400^{\circ}C$ for $30^{\circ}C$ minutes in a vacuum furnace. Homogeneous distribution of Zn particles of size was obtained by the zincate treatment with pH 13 ~ 13.5, solution concentration of 15 ~ 25% at room temperature. The plating rates for both Ni-P and Au electroless plating steps increased with increasing the plating temperature and pH. The main crystallization planes of the plated Au were found to be (111) a pH 7 and (200) and (111) at pH 9 independent of the annealing temperature.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.33-38
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• 2007

We studied a bonding at low temperature using polymer bump and Non-Conductive Adhesive (NCA), and studied the reliability of the polymer bump/Al pad joints. The polymer bumps were formed on oxidized Si substrates by photolithography process, and the thin film metals were formed on the polymer bumps using DC magnetron sputtering. The substrate used was AL metallized glass. The polymer bump and Al metallized glass substrates were joined together at $80^{\circ}C$ under various pressure. Two NCAs were applied during joining. Thermal cycling test ($0^{\circ}C-55^{\circ}C$, cycle/30 min) was carried out up to 2000 cycles to evaluate the reliability of the joints. The bondability was evaluated by measuring the contact resistance of the joints through the four point probe method, and the joints were observed by Scanning Electron Microscope (SEM). The contact resistance of the joints was $70-90m{\Omega}$ before the reliability test. The joints of the polymer bump/Al pad were damaged by NCA filler particles under pressure above 200 MPa. After reliability test, some joints were electrically failed since thinner metal layers deposited at the edge of bumps were disconnected.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.11a
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• pp.144-145
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• 2017

최근 전자 기기의 크기가 줄어들고 PCB의 사이즈와 반도체 패키지의 크기가 소형화되어 플립 칩 본딩(Flip chip bonding) 기술을 적용한 반도체 패키지 방식이 점점 늘어나고 있다. 이에 따라 PCB와 반도체 칩 사이를 연결하기 위해 응용되던 BGA(Ball Grid Array)에 핀 배열 대신 사용되는 범프(Bump)를 50um 이내의 초미세 범프로 만들어 일정한 배열을 유지하는 것이 중요하다. 또한 초미세 범프의 모양과 품질이 패키지 수율과 밀접하게 연관되기 때문에 이를 검사할 수 있는 기술이 필수적이다. 이에 본 논문은 초미세 범프측정을 할 수 있는 시스템 개발을 위한 측정 대상의 특징과 사용할 수 있는 광학계를 분석하였고, 획득된 영상을 가지고 딥러닝을 적용하여 정확하게 불량여부를 판별할 수 있는 초미세 범프 측정 시스템을 고안하였다.

• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• ETRI Journal
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• v.33 no.4
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• pp.637-640
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• 2011

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder-on-pad technology of the fine-pitch flip-chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 ${\mu}m$ in one direction.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.31-31
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• 2015

본 연구는, TAB(Tape Automated Bonding)접속이나 Flip Chip 접속에 의한 패캐징을 실현시키기 위해, 실리콘 웨이퍼 표면에 구리 필러 및 주석 합금을 전기 도금법으로 형성하는 전기 접점용 범프에 관한 것이다. 본 연구에서는, 균일 범프 두께, 범프 표면의 균일화, 범프 내의 보이드 발생 문제 해결, 균일한 합금 조성 및 도금 속도의 고속화를 위해, Cu 도금액 및 Sn-Ag 도금액의 첨가제에 의한 표면 형상의 제어를 중심으로 그 성능에 대해 보고한다.

• Journal of Surface Science and Engineering
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• v.50 no.3
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• pp.170-176
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• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.