• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Communications of the Korean Mathematical Society
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• v.6 no.2
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• pp.261-266
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• 1991

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.6 no.2
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• pp.75-84
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• 2002

Using good properties of an optimal normal basis of type I in a finite field ${\mathbb{F}}_{2^m}$, we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing $xy^2$. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware architecture for a bit serial multiplication of two elements in ${\mathbb{F}}_{2^m}$.

• Korean Journal of Mathematics
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• v.22 no.3
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• pp.455-462
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• 2014

Let D be an integral domain with Spec(D) finite, K the quotient field of D, [D,K] the set of rings between D and K, and SFc(D) the set of semistar operations of finite character on D. It is well known that |Spec(D)| ${\leq}$ |SFc(D)|. In this paper, we prove that |Spec(D)| = |SFc(D)| if and only if D is a valuation domain, if and only if |Spec(D)| = |[D,K]|. We also study integral domains D such that |Spec(D)|+1 = |SFc(D)|.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.527-532
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• 2021

In this paper, we propose an efficient finite field computation method for Rainbow algorithm, which is the only multivariate quadratic-equation based digital signature among the current US NIST PQC standardization Final List algorithms. Recently, Chou et al. proposed a new efficient implementation method for Rainbow on the Cortex-M4 environment. This paper proposes a new multiplication method over the finite field that can reduce the number of XOR operations by more than 13.7% compared to the Chou et al. method. In addition, a multiplicative inversion over that can be performed by a 4x4 matrix inverse instead of the table lookup method is presented. In addition, the performance is measured by porting the software to which the new method was applied onto RaspberryPI 3B+.

• Journal of Magnetics
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• v.8 no.2
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• pp.79-84
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• 2003

Finite element analysis showed that strong magnetic fields were distributed around the arc furnace where the strongest magnetic fields were generated around the three phase cables. The second and third strongest fields near the arc furnace were found to be generated around the electrodes and the mast-arms, respectively. The generated field intensities were greatly influenced by the mast arm structure of the arc furnace as well as the phase differences and operation currents of the supplied power, Magnetic field decay patterns around the arc furnace could be smoothly fitted by this equation of exponential formula, H=H$0_$+Ae$^{\frac{r}{t}}$. These results revealed that magnetic field intensities around the arc furnace could be estimated at any 3-dimensional position using finite element method (FEM).

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 1999.02a
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• pp.81-84
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• 1999

The purpose of this paper is to find the magnetic field distribution inside the motor in order to find out if the high-Tc superconducting tapes operate stably in actual motor operation. With this gola, magnetic field distribution in a detailed model of the actual motor was analyzed through F.E.M. (Finite Element Method). As a result, it has been proved that the high-Tc superconducting tapes can withstand 4 A of current with stability. 4 A was the amount of current needed to achieve 600 A ·turns which is required by the previous simulation aimed at developing this motor. Also, it has been observed that the flux damper reduces armature reactance during the motor operation and during load changes, helping the stable motor operation. But, it was observed that the flux damper generates loss by means of leakage flux and this decreases the output of the motor by about 5%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.145-151
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• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.