• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.639-644
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• 2011

By the development of the information superhighway, the current data communication system can be exchanged data quickly and precisely between subscribers. In this paper, LVTTL(Low Voltage Transistor Transistor Logic), Using the fundamental one logic at several kinds of used in communication systems, the LVTTL transmission characteristics were measured by according to the change data transfer rate and the transmission line length. Because the transmission line length required on the current system is 30cm, We analysed LVTTL data transfer characteristics according to the transmission line length required on the current system. The amplitude level of LVTTL at 10Mbps is 3V and 50Mbps is 2.2V and 100Mbps is 2V and 125Mbps is 1.5V and 150Mbps is 1.4V. The length of transmission line 30cm was stable state up to 100Mbps data transfer rate.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1535-1544
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• 2017

Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.136-144
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• 2021

The purpose of this study was to develop and verify a precision transmission error measurement system for a gear pair. The transmission error measurement system of the gear pair was developed as a measurement unit, signal processing unit, and signal analysis unit. The angular displacement for calculating the transmission error of the gear pair was measured using an encoder. The signal amplification, interpolation, and transmission error calculation of the measured angular displacement were conducted using a field-programmable gate array (FPGA) and a real-time processor. A high-pass filter (HPF) was applied to the calculated transmission error from the real-time processor. The transmission error measurement test was conducted using a gearbox, including the master gear pair. The same test was repeated three times in the clockwise and counterclockwise directions, respectively, according to the load conditions (0 - 200 N·m). The results of the gear transmission error tests showed similar tendencies, thereby confirming the stability of the system. The measured transmission error was verified by comparing it with the transmission error analyzed using commercial software. The verification showed a slight difference in the transmission error between the methods. In a future study, the measurement and analysis method of the developed precision transmission error measurement system in this study may possibly be used for gear design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.219-220
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• 2016

A power management system (PMS) has been an important part in a ship integrated control system. To evaluate a PMS for a liquefied natural gas carrier (LNGC), this research proposes a real-time hardware-in-the-loop simulation (HILS), which is composed of major component models such as turbine generator, diesel generator, governor, circuit breaker, and 3-phase loads on MATLAB/Simulink. In addition, FPGA based control console and main switchboard (MSBD) are constructed in order to develop an efficient control and a similar real environment in an LNGC PMS. A comparative study on the performance evaluation of PMS functions is conducted using two test cases for sharing electric power to consumers in an LNGC. The result shows that the proposed system has a high verification capability for the operating function and failure insertion evaluation as a PMS simulator.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.