• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.197-204
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• 2010

An effective integration of web-based learning environment and mobile device technology is considered as a new challenge to the developers. The screen size, however, of the mobile device is too small, and its performance is too inferior. Due to the foregoing limit of mobile technology, displaying bulk data on the mobile screen, such as a cyber lecture accompanied with real-time image transmission on the web, raises a lot of problems. Users have difficulty in recognizing learning contents exactly by means of a mobile device, and continuous transmission of video stream with bulky information to the mobile device arouses a lot of load for the mobile system. Thus, an application which is developed to be applied in PC is improper to be used for the mobile device as it is, a player which is fitting for the mobile device should be developed. Accordingly, this paper suggests mobile presentation using transcoding techniques of the field concerned. To display continuous video frames of learning image, such as a cyber lecture or remote lecture, by means of a mobile device, the performance difference between high-resolution digital image and mobile device should be surmounted. As the transcoding techniques to settle the performance difference causes damage of image quality, high-quality image may be guaranteed by application of trial and error between transcoding and selected learning resources.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Journal of the Korea Society of Computer and Information
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• v.27 no.3
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• pp.63-69
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• 2022

In this paper, we propose a new GPU-based framework for quickly calculating adaptive and continuous SDF(Signed distance fields), and examine cases related to rendering/collision processing using them. The quadtree constructed from the triangle mesh is transferred to the GPU memory, and the Euclidean distance to the triangle is processed in parallel for each thread by using it to find the shortest continuous distance without discontinuity in the adaptive grid space. In this process, it is shown through experiments that the cut-off view of the adaptive distance field, the distance value inquiry at a specific location, real-time raytracing, and collision handling can be performed quickly and efficiently. Using the proposed method, the adaptive sign distance field can be calculated quickly in about 1 second even on a high polygon mesh, so it is a method that can be fully utilized not only for rigid bodies but also for deformable bodies. It shows the stability of the algorithm through various experimental results whether it can accurately sample and represent distance values in various models.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.11
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• pp.319-328
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• 2023

Unlike cloud computing, edge computing technology analyzes and judges data close to devices and users, providing advantages such as real-time service, sensitive data protection, and reduced network traffic. EdgeX Foundry, a representative open source of edge computing platforms, is an open source-based edge middleware platform that provides services between various devices and IT systems in the real world. EdgeX Foundry provides a service for handling camera devices, along with a service for handling existing sensed data, which only supports simple streaming and camera device management and does not store or process image data obtained from the device inside EdgeX. This paper presents a technique that can store and process image data inside EdgeX by applying some of the services provided by EdgeX Foundry. Based on the proposed technique, a service pipeline for object detection services used core in the field of autonomous driving was created for experiments and performance evaluation, and then compared and analyzed with existing methods.

• The KIPS Transactions:PartA
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• v.11A no.4
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• pp.235-242
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• 2004

When manufacturing information and communication device that consists of lots of part, it is important to improve the quality of the produced system by inspecting the system accurately and exclude the defected part. In case of LCD which is recently in a great demand, the inspection process of the nut which bonds the back frame to protect the LCD panel has to be done by human labor. It highly required an automatic inspection system which can inspect the nut without wasting human resources. In this paper, we describe the process of developing a system which automatically inspect the status of nuts inserted during the manufacturing of LCD. The nut inspection vision system developed measures the number of nut's spiral, the distance between pitches, the width of a pitch, and the inside diameter of nut. We have adopted lens with high magnifying power and calibration tool and intended to produce automatic lighting for maintaining a stable environment for a high precision system. We also developed the algorithms for analyzing the nut. We apply the system to real factory field and verify that it is better than the man power in terms of error rate.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.3
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• pp.133-138
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• 2018

VR technology is a technology that allows a user to experience virtual reality close to reality by wearing an HMD (Head Mounted Display) device. Recently, as the interest in VR technology increases due to the 4th industrial revolution, various HMD devices are spreading. As a result, VR technology is being rapidly applied to various fields, but many of them still experience VR nausea. VR nausea is caused mainly by visual factors, unlike motion nausea, such as car nausea, sea nausea, and air nausea. Such occurrence of VR nausea may be caused by the characteristics of visual information of VR video contents, the hardware characteristics of HMD devices blocking the external visual field, or the physical specificity of individuals, and it is difficult to distinguish the causes. In this paper, we aim to analyze the characteristics of Visually Induced Motion Nausea images focusing on VR video content, which is the cause of VR nausea, in order to search for minimization of Cyber sickness occurrence.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.1
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• pp.80-87
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• 2012

We have developed the ATE(Automatic Test Equipment) system for the performance test of pre-amplifier of thermal imaging devices. The device regenerates the electronic signals of photon detection module which is normally in weak energy, for the image signals processing. Previous ATE system was primarily and actively developed in the field of semiconductor devices quality parts inspection. Recently, it has been studied in the field of performance testing of equipment. In the field of thermal performance test equipment, however, it lacks the study of ATE compared to other areas, which causes the maintenance related to the core of military thermal imaging system maintenance to be limited. In this paper, a new study of ATE in the field of thermal imaging system is done. It is designed to be used universally for the ATE system with different types of circuit card of thermal imaging system by adopting matrix relays. Using the developed ATE measuring the pre-amplifier amplitude, an average amplified amplitude of 2.71Vpp was measured which confirms that it is within the range of theoretical analysis and also verifies the good performance of the developed ATE.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.588-591
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• 2009

In ubiquitous computing GIS services, it is possible to use the spatio-temporal data anytime through the mobile device. GIS services regularly update use the latest spatio-temporal data to provide the most suitable services. For this situation, update data is distributed to CD or wired networks update services. However, this method has problem to propagate update data to users as taking long time. In this paper, suggests a synchronization system which propagate update data to users for reducing processing time efficiently. This synchronization system collects update data in the field and synchronizes server with collected data to use mobile devices by real time. For this system, I design and materialize synchronization module which updates update data and wireless network module.