• 제목/요약/키워드: Field Effect Mobility

검색결과 517건 처리시간 0.027초

게이트 절연막에 사용된 점착층에 대한 영향 (Effect of Adhesion Layer on Gate Insulator)

  • 이동현;형건우;표상우;김영관
    • 한국전기전자재료학회논문지
    • /
    • 제19권4호
    • /
    • pp.357-361
    • /
    • 2006
  • The electrical performances of organic thin-film transistors (OTFTs) have been improved for the last decade. In this paper, it was demonstrated that the electrical characteristics of the organic thin film transistors (OTFTs) were improved by using polymeric material as adhesion layer on gate insulator. We have investigated OTFTs with polyimide adhesion layer which was fabricated by vapor deposition polymerization (VDP) processing and formed by co-deposition of 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride and 4,4'-oxydianiline. It was found that the OTFTs with adhesion layer showed better electrical characteristics than with bare layer because of good matching between semiconductor and gate insulator. Our devices of performance are field effect mobility of $0.4cm^2/Vs$, threshold voltage of -0.8 V and on-off current ratio of $10^6$. In addition, to improve the electrical characteristics of OTFT, we have reduced the thickness of adhesion layer up to a few nanometrs.

Effects of Stress Mismatch on the Electrical Characteristics of Amorphous Silicon TFTs for Active-Matrix LCDs

  • Lee, Yeong-Shyang;Chang, Jun-Kai;Lin, Chiung-Wei;Shih, Ching-Chieh;Tsai, Chien-Chien;Fang, Kuo-Lung;Lin, Hun-Tu;Gan, Feng-Yuan
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
    • /
    • pp.729-732
    • /
    • 2006
  • The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

  • PDF

활성층 두께 및 열처리 온도에 따른 비정질 인듐갈륨징크옥사이드 박막트랜지스터의 전기적 특성 변화 (Electrical Properties Depending on Active Layer Thickness and Annealing Temperature in Amorphous In-Ga-Zn-O Thin-film Transistors)

  • 백찬수;임기조;임동혁;김현후
    • 한국전기전자재료학회논문지
    • /
    • 제25권7호
    • /
    • pp.521-524
    • /
    • 2012
  • We report on variations of electrical properties with different active layer thickness and post-annealing temperature in amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). In particular, subthreshold swing (SS) of the IGZO-TFTs was improved as increasing the active layer thickness at an given post-annealing temperature, accompanying the negative shift in turn-off voltage. However, as increasing post-annealing temperature, only turn-off voltage was shifted negatively with almost constant SS value. The effect of the active layer thickness and post-annealing temperature on electrical properties, such as SS, field effect mobility and turn-off voltage in IGZO-TFTs has been explained in terms of the variation of trap density in IGZO channel layer and at gate dielectric/IGZO interface.

OTFT의 게이트 절연막에 사용된 점착층에 대한 영향 (The Effect of Adhesion layer on Gate Insulator for OTFTs)

  • 이동현;형건우;표상우;김정수;김영관
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
    • /
    • pp.70-71
    • /
    • 2005
  • The electrical performances of organic thin-film transistors (OTFTs) have been improved for the last decade. In this paper, it was demonstrated that the electrical characteristics of the organic thin film transistors (OTFTs) were improved by using polymeric material as adhesion layer on gate insulator. We have investigated OTFTs with polyimide adhesion layer which was fabricated by vapor deposition polymerization (VDP) processing and formed by co-deposition of 6FDA and ODA. It was found that the OTFTs with adhesion layer showed better electrical characteristics than with bare layer because of good matching between semiconductor and gate insulator. Our devices of performance are field effect mobility of $0.4cm^2$/Vs, threshold voltage of -0.8 V and on-of current ratio of $10^6$. In addition, to improve the electrical characteristics of OTFT, we have reduced the thickness of adhesion layer up to a few nanometrs.

  • PDF

음 바이어스 스트레스를 받은 졸-겔 IGZO 박막 트랜지스터를 위한 효과적 양 바이어스 회복 (Effective Positive Bias Recovery for Negative Bias Stressed sol-gel IGZO Thin-film Transistors)

  • 김도경;배진혁
    • 센서학회지
    • /
    • 제28권5호
    • /
    • pp.329-333
    • /
    • 2019
  • Solution-processed oxide thin-film transistors (TFTs) have garnered great attention, owing to their many advantages, such as low-cost, large area available for fabrication, mechanical flexibility, and optical transparency. Negative bias stress (NBS)-induced instability of sol-gel IGZO TFTs is one of the biggest concerns arising in practical applications. Thus, understanding the bias stress effect on the electrical properties of sol-gel IGZO TFTs and proposing an effective recovery method for negative bias stressed TFTs is required. In this study, we investigated the variation of transfer characteristics and the corresponding electrical parameters of sol-gel IGZO TFTs caused by NBS and positive bias recovery (PBR). Furthermore, we proposed an effective PBR method for the recovery of negative bias stressed sol-gel IGZO TFTs. The threshold voltage and field-effect mobility were affected by NBS and PBR, while current on/off ratio and sub-threshold swing were not significantly affected. The transfer characteristic of negative bias stressed IGZO TFTs increased in the positive direction after applying PBR with a negative drain voltage, compared to PBR with a positive drain voltage or a drain voltage of 0 V. These results are expected to contribute to the reduction of recovery time of negative bias stressed sol-gel IGZO TFTs.

Cross-Linked PVP 게이트 유기 박막트랜지스터 (Organic Thin Film Transistors with Cross-Linked PVP Gates)

  • 장지근;오명환;장호정;김영섭;이준영;공명선;이영관
    • 마이크로전자및패키징학회지
    • /
    • 제13권1호통권38호
    • /
    • pp.37-42
    • /
    • 2006
  • 유기 박막트랜지스터(OTFTs)제작에서 PVP-게이트 절연막의 형성과 처리가 소자성능에 미치는 영향을 조사하였다. 유기 게이트 용액의 제조에서는 polyvinyl 계열의 PVP(poly-4-vinylphenol)를 용질로, PGMEA (propylene glycol monomethyl ether acetate)를 용매로 사용하였다. 또한 열경화성 수지인 poly(melamine-co-formaldehyde)를 경화제로 사용하여 유기 절연막의 cross-link를 시도하였다. MIM 시료의 전기적 절연 특성을 측정한 결과, PVP-기반 유기 절연막은 용액의 제조에서 PGMEA에 대한 PVP와 poly (melamine-co-formaldehyde)의 농도를 증가시킬수록 낮은 누설전류 특성을 나타내었다. OTFT 제작에서는 PGMEA에 대해 PVP를 20 wt%로 섞은 PVP(20 wt%) copolymer와 5 wt%와 10 wt%의 poly(melamine-co-formaldehyde)를 경화제로 추가한 cross-linked PVP(20 wt%)를 게이트 유전 재료로 사용하였다. 제작된 트랜지스터들에서 전계효과 이동도는 5 wt % cross-linked PVP(20 wt%) 소자에서 $0.31cm^2/Vs$로, 그리고 전류 점멸비는 10 wt% cross-linked PVP(20 wt%) 소자에서 $1.92{\times}10^5$으로 가장 높게 나타났다.

  • PDF

염소(Chlorine)가 도입된 $SiO_2/Si$ 계면을 가지는 게이트 산화막의 특성 분석 (Characterization of Gate Oxides with a Chlorine Incorporated $SiO_2/Si$ Interface)

  • 유병곤;유종선;노태문;남기수
    • 한국진공학회지
    • /
    • 제2권2호
    • /
    • pp.188-198
    • /
    • 1993
  • 두께가 6~10 nm인 게이트 산화막의 계면에 염소(Cl)를 도입시킨 n-MOS capacitor 및 n-MOSFET을 제잘하여 물성적인 방법(SIMS, ESCA)과 전기적인 방법에 의해서 소자의 특성을 분석, 평가하였다. Last step TCA법을 이용하여 성장시킨 산화막은 No TCA법으로 성장시킨 것보다 mobility가 7% 정도 증가하였고, 결함 밀도도 감소하였다. Time-zero-dielectric-breakdown(TZDB)으로 측정한 결과, Cl를 도입한 막의 파괴 전계(breakdon field)는 18 MV/cm인데, 이것은 Cl을 도입하지 않은 것보다 약 0.6 MV/cm 정도 높은 값이다. 또한 time-dependent-dielectric-breakdown(TDDB) 결과로부터 수명이 20년 이상인 것으로 평가되었고, hot carrier 신뢰성 측정으로부터 평가한 소자의 수명도 양호한 것으로 나타났다. 이상의 결과에서 Cl을 계면에 도입시킨 게이트 산화막을 가진 소자가 좋은 특성을 나타내고 있으므로 Last step TCA법을 종래의 산화막 성장 방법 대신에 사용하면 MOSFET 소자의 새로운 게이트 절연막 성장법으로서 대단히 유용할 것으로 생각된다.

  • PDF

CuCl2 노출에 의해 유도되는 제브라피시의 행동과 내분비계의 변화 (Exposure to Copper (II) Chloride Induces Behavioral and Endocrine Changes in Zebrafish)

  • Sung, Jiwon;Lee, Jeongwon;Lee, Seungheon
    • 생명과학회지
    • /
    • 제30권4호
    • /
    • pp.321-330
    • /
    • 2020
  • 본 연구의 목표는 CuCl2가 지브라피시에 미치는 영향을 조사하는 것이다. CuCl2에 대한 지브라피시의 반수치사농도를 조사하기 위하여 각기 다른 시간에 따른 농도를 설정하여 노출시켰다. 본 연구에서는 스트레스 반응의 증가를 보기 위하여 whole-body cortisol level 측정과 행동약리학적 변화를 측정하기 위해서 open field test와 novel tank test를 실시하였다. Whole-body cortisol의 sample을 수집하거나 행동실험을 실시하기 전에 CuCl2 또는 vehicle을 1시간 동안 처리하였다. CuCl2의 반수치사농도는 24시간, 48시간, 96시간에서 각각 30.3, 25.3, 14.8 ㎍/l으로 측정되었다. CuCl2에 노출된 지브라피시의 novel tank test의 결과는 총 이동거리, 움직이는 시간 그리고 속도는 유의성이 있게 감소한 반면, turn angle은 최고농도에서 유의성이 있게 증가하였다(p<0.05). 다른 행동실험인 open field test의 결과에서도 총 이동거리, 움직이는 시간 속도가 CuCl2의 노출에 의해서 감소하였으며, turn angle과 meandering이 유의하게 증가하였다(p<0.05). CuCl2에 노출된 지브라피시의 whole-body cortisol은 1.5 or 15 ㎍/l의 농도에서는 유의하게 증가하였으나, 150 ㎍/l의 농도에서는 유의성 있는 변화를 발견하지 못하였다(p<0.05). 본 연구의 결과는 CuCl2의 노출이 지브라피시에서 치사율 증가, 행동 및 내분비의 변화 등을 포함하는 독성 반응을 야기하는 것을 나타낸다.

Design and Analysis of AlGaN/GaN MIS HEMTs with a Dual-metal-gate Structure

  • Jang, Young In;Lee, Sang Hyuk;Seo, Jae Hwa;Yoon, Young Jun;Kwon, Ra Hee;Cho, Min Su;Kim, Bo Gyeong;Yoo, Gwan Min;Lee, Jung-Hee;Kang, In Man
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제17권2호
    • /
    • pp.223-229
    • /
    • 2017
  • This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.

High Performance p-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method

  • U, Myeonghun;Han, Young-Joon;Song, Sang-Hun;Cho, In-Tak;Lee, Jong-Ho;Kwon, Hyuck-In
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제14권5호
    • /
    • pp.666-672
    • /
    • 2014
  • We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.