• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.141-157
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• 2001

Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

• 마이크로전자및패키징학회지
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• 제30권3호
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• pp.73-77
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• 2023

본 연구에서는 서로 다른 강유전성 물질을 활용하여 Multi-level FeRAM (Ferroelectrics random access memory) 소자에 대한 구조를 제시하였으며, 이를 검증하기 위해 Simulation을 통한 C-V 분석을 수행하였습니다. Multi-level 소자를 구현하기 위해 두 가지 서로 다른 물성을 가진 강유전체를 동일한 하부 전극 위에 나란히 증착하고, 이후 게이트 전극을 위에 올린 MFM (Multi-Ferroelectric Material) 구조를 제안하였습니다. 두 강유전체가 서로 다른 전압 조건에서 분극 현상 (Polarization)을 나타내는 것을 바탕으로, 두 개의 물질 중 한 개만 polarization 되었을 때와 두 개 모두 polarization 되었을 때의 상황을 C-V peak 분석을 통해 확인하여 Multi-level 동작을 구현할 수 있음을 확인하였습니다. 더불어, 제시한 구조를 반도체 제조 공정을 활용하여 구현하는 방법을 공정 simulation을 통해 검증하였습니다. 이러한 결과는 하나의 메모리 셀에서 여러 상태 값을 저장할 수 있음을 의미하며, 이는 메모리의 집적도를 크게 향상시킬 수 있는 새로운 구조체로서의 가능성을 의미합니다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.258-261
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• 2011

A ferroelectric $(Bi,La)_4Ti_3O_{12}$ (BLT) thin film fabricated by the pulsed-DC sputtering method was evaluated on a cell structure to check its compatibility to high density ferroelectric random access memory (FeRAM) devices. The BLT composition in the sputtering target was $Bi_{4.8}La_{1.0}Ti_{3.0}O_{12}$. Firstly, a BLT film was deposited on a buried Pt/$IrO_x$/Ir bottom electrode stack with W-plug connected to the transistor in a lower place. Then, the film was finally crystallized at $700^{\circ}C$ for 30 seconds in oxygen ambient. The annealed BLT layer was found to have randomly oriented and small ellipsoidal-shaped grains (long direction: ~100 nm, short direction: ~20 nm). The small and uniform-sized grains with random orientations were considered to be suitable for high density FeRAM devices.

• 한국세라믹학회지
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• 제41권4호
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• pp.273-276
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• 2004

Report ferroelectric memories based on 0.35$\mu\textrm{m}$ CMOS technology ensuring ten-year retention and imprint at 175$^{\circ}C$. This excellent reliability resulted from newly developed BT-based ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen. The superior reliabilities at high temperature of ferroelectric memories using BT-based films are due to the random orientation by special bake treatments.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1996년도 재료학회 추계학술발표회
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• pp.1-1
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• 1996

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1448-1449
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• 2006

Pb(Zr,Ti)$O_3$ is one of the most attractive ferroelectric materials for realizing the FeRAM due to its higher remanant polarization and the ability to withstand higher coercive fields. Generally, the ferroelectric materials were patterned by a plasma etching process for high-density FeRAM. The applicable possibility of CMP process to pattern Pb(Zr,Ti)$O_3$ instead of plasma etching process was investigated in our previous study for improvement of an angled sidewall which prevents the densification of ferroelectric memory and is apt to receive the plasma damage. Our previous study showed that good removal rate with the excellent surface roughness compared to plasma etching process were obtained by CMP process for the patterning of Pb(Zr,Ti)$O_3$. The suitable selectivity to TEOS without any damage to the structural property of Pb(Zr,Ti)$O_3$ was also guaranteed. In this study, the removal mechanism of $Pb_{1.1}(Zr_{0.52}Ti_{0.48})O_3$ coated by sol-gel method was investigated. Surface analysis of polished specimens at the best and worst conditions was carried out by XPS.

• 한국재료학회지
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• 제30권2호
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• pp.99-104
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• 2020

Recent discoveries of ferroelectric properties in ultrathin doped hafnium oxide (HfO₂) have led to the expectation that HfO₂ could overcome the shortcomings of perovskite materials and be applied to electron devices such as Fe-Random access memory (RAM), ferroelectric tunnel junction (FTJ) and negative capacitance field effect transistor (NC-FET) device. As research on hafnium oxide ferroelectrics accelerates, several models to analyze the polarization switching characteristics of hafnium oxide ferroelectrics have been proposed from the domain or energy point of view. However, there is still a lack of in-depth consideration of models that can fully express the polarization switching properties of ferroelectrics. In this paper, a Zr-doped HfO₂ thin film based metal-ferroelectric-metal (MFM) capacitor was implemented and the polarization switching dynamics, along with the ferroelectric characteristics, of the device were analyzed. In addition, a study was conducted to propose an applicable model of HfO₂-based MFM capacitors by applying various ferroelectric switching characteristics models.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.103-104
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• 2006

$Pb(Zr,Ti)O_3(PZT)$ is very attractive ferroelectric materials for ferroelectric random access memory (FeRAM) applications because of its high polarization ability and low process temperature. However, Chemical Mechanical Polishing (CMP) pressure and velocity must be carefully adjusted because FeRAM shrinks to high density devices. The contaminations such as slurry residues due to the absence of the exclusive cleaning chemicals are enough to influence on the degradation of PZT thin film capacitors. The surface characteristics of PZT thin film were investigated by the change of process parameters and the cleaning process. Both the low CMP pressure and the cleaning process must be employed, even if the removal rate and the yield were decreased, to reduce the fatigue of PZT thin film capacitors fabricated by damascene process. Like this, fatigue characteristics were partially controlled by the regulation of the CMP process parameters in PZT damascene process. And the exclusive cleaning chemicals for PZT thin films were developed in this work.