• 한국통신학회논문지
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• 제22권8호
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• pp.1823-1832
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• 1997

본 논문은 유한 상태 기계 모델로 표현된 통신 프로토콜의 시험항목에 대한 오류 발견 능력 분석 방법을 제시한다. 시험항목에 대한 오류 발견 능력의 평가는 생성된 시험항목으로 어느 정도까지 오류를 발견해 낼 수 있는지를 측정하는 것이다. 시험항복의 오류 발견 능력 평가 방법은 주로 수학적 분석과 시뮬레이션을 이용한 방법이 사용되고 있다. 본 논문에서는 동신 프로토콜 시험항목의 오류 발견 능력 분석음 위해 시뮬레이터를 설계, 구현하였다. Inres 프로토콜을 시뮬레이터에 적용한 결과, 출력 오류와 상태 병합. 분리 오류는 100%의 높은 오류 발견율을 보였다. 구현된 오류 발견 능력 분석 시뮬레이터는 다양한 프로토콜에 적용 가능함으로써 새로운 오류 발견 능력 분석 도구로 사용될 수 있다.

• Journal of Advanced Marine Engineering and Technology
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• 제22권5호
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2000년도 춘계학술대회 논문집
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• pp.330-335
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• 2000

Faults detection and containment requirements are typically allocated from a top-level specification as a percentage of total faults detection and containment, weighted by failure rate. This faults detection and containments are called as a fault coverage. The fault coverage requirements are typically allocated identically to all units in the system, without regard to complexity, cost of implementation or failure rate for each units. In this paper a simple methodology and mathematical model to support the allocation of system fault coverage rates to lower-level units by considering the inherent differences in reliability is presented. The models are formed as a form of constrained optimization. The objectives and constraints are modeled as a linear form and this problems are solved by linear programming. It is identified by simulation that the proposed solving methods for these problems are effective to such requirement allocating.

• Nuclear Engineering and Technology
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• 제44권4호
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• pp.421-428
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• 2012

Analog instrument and control systems in nuclear power plants have recently been replaced with digital systems for safer and more efficient operation. Digital instrument and control systems have adopted various fault-tolerant techniques that help the system correctly and safely perform the specific required functions regardless of the presence of faults. Each fault-tolerant technique has a different inspection period, from real-time monitoring to monthly testing. The range covered by each faulttolerant technique is also different. The digital instrument and control system, therefore, adopts multiple barriers consisting of various fault-tolerant techniques to increase the total fault detection coverage. Even though these fault-tolerant techniques are adopted to ensure and improve the safety of a system, their effects on the system safety have not yet been properly considered in most probabilistic safety analysis models. Therefore, it is necessary to develop an evaluation method that can describe these features of digital instrument and control systems. Several issues must be considered in the fault coverage estimation of a digital instrument and control system, and two of these are addressed in this work. The first is to quantify the fault coverage of each fault-tolerant technique implemented in the system, and the second is to exclude the duplicated effect of fault-tolerant techniques implemented simultaneously at each level of the system's hierarchy, as a fault occurring in a system might be detected by one or more fault-tolerant techniques. For this work, a fault injection experiment was used to obtain the exact relations between faults and multiple barriers of faulttolerant techniques. This experiment was applied to a bistable processor of a reactor protection system.

• 품질경영학회지
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• 제21권1호
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• pp.78-95
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• 1993

The art of designing and analyzing fault-tolerant computers is surveyed with special emphasis on problems of analyzing the behavior of computers that have autonomous repair capability. The survey covers the following topics : (1) general issues in computer reliability, (2) fault-tolerance state relations and requirements, (3) computational hierarchy, (4) fault characteristics, (5) fault diagnosis, (6) fault-tolerance schemes for logic network and machines, (7) fault-coverage effects, and (8) fault-tree analysis of coverage. This paper does not include techniques for verifying nonredundant hardware or system software designs or for verifying the correctness of application programs.

• 전자공학회논문지C
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• 제35C권4호
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• pp.11-20
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• 1998

Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.

• 대한전자공학회논문지SD
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• 제38권4호
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• pp.266-276
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• 2001

빠른 반도체 기술의 발전으로 인하여 VLSI 회로의 복잡도는 크게 증가하고 있다. 그래서 복잡한 회로를 테스팅하는 것은 아주 어려운 문제로 대두되고 있다. 또한 집적회로의 증가된 집적도로 인하여 여러 가지 형태의 고장이 발생하게 됨으로써 테스팅은 더욱 중요한 문제로 대두되고 있다. 이제까지 일반적으로 지연 고장 테스팅에 대한 신뢰도는 가정된 고장의 개수에 대한 검출된 고장의 개수로 표현되는 전통적인 고장 검출율로서 평가되었다. 그러나 기존의 교장 검출율은 고장 존재의 유무만을 고려한 것으로써 실제의 지연 고장 테스팅에 대한 신뢰도와는 거리가 있다. 지연 고장 테스팅은 고착 고장과는 달리 경로의 진행 지연과 지연 결함 크기 그리고 시스템 동작 클럭 주기에 의존하기 때문이다. 본 논문은 테스트 중인 경로의 진행 지연과 지연 결함 크기를 고려한 새로운 고장 검출율 메트릭으로서지연 결함 고장 검출율(delay defect fault coverage)을 제안하였으며, 지연 결함 고장 검출율과 결함 수준(defect level)과의 관계를 분석하였다.

• International Journal of Reliability and Applications
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• 제8권1호
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• pp.53-66
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• 2007

This paper proposes a new non-homogeneous Poisson process software reliability growth model based on the coverage information. The new model incorporates the coverage information in the fault detection process by assuming that only the faults in the covered constructs are detectable. Since the coverage growth behavior depends on the testing strategy, the fault detection process is first modeled for the general testing strategy and then realized for the uniform testing. Finally the model for the uniform testing is empirically evaluated by applying it to real data sets.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.