• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1823-1832
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• 1997

In this ppaer, fault coverage analysis of a conformance test case for communication protocols, specified as a deterministic finite state machine(DFSM) is presented. The fault coverage analysis of a test case is defined by measuring the extent of the faults detected using a generated test case. The method that evaluates fault coverage analysis for a test case, has been researched by arithmetic analysis and simulation. In this paper, we designed and implemented a simulator for fault coverage analysis of a communication protocol teat case. With this result for Inres protocol, output fault and state merge and split fault have a high fault coverage of 100%. This simulator can be widely used with new fault coverage analysis tools by applying it to various protocols.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.330-335
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• 2000

Faults detection and containment requirements are typically allocated from a top-level specification as a percentage of total faults detection and containment, weighted by failure rate. This faults detection and containments are called as a fault coverage. The fault coverage requirements are typically allocated identically to all units in the system, without regard to complexity, cost of implementation or failure rate for each units. In this paper a simple methodology and mathematical model to support the allocation of system fault coverage rates to lower-level units by considering the inherent differences in reliability is presented. The models are formed as a form of constrained optimization. The objectives and constraints are modeled as a linear form and this problems are solved by linear programming. It is identified by simulation that the proposed solving methods for these problems are effective to such requirement allocating.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.421-428
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• 2012

Analog instrument and control systems in nuclear power plants have recently been replaced with digital systems for safer and more efficient operation. Digital instrument and control systems have adopted various fault-tolerant techniques that help the system correctly and safely perform the specific required functions regardless of the presence of faults. Each fault-tolerant technique has a different inspection period, from real-time monitoring to monthly testing. The range covered by each faulttolerant technique is also different. The digital instrument and control system, therefore, adopts multiple barriers consisting of various fault-tolerant techniques to increase the total fault detection coverage. Even though these fault-tolerant techniques are adopted to ensure and improve the safety of a system, their effects on the system safety have not yet been properly considered in most probabilistic safety analysis models. Therefore, it is necessary to develop an evaluation method that can describe these features of digital instrument and control systems. Several issues must be considered in the fault coverage estimation of a digital instrument and control system, and two of these are addressed in this work. The first is to quantify the fault coverage of each fault-tolerant technique implemented in the system, and the second is to exclude the duplicated effect of fault-tolerant techniques implemented simultaneously at each level of the system's hierarchy, as a fault occurring in a system might be detected by one or more fault-tolerant techniques. For this work, a fault injection experiment was used to obtain the exact relations between faults and multiple barriers of faulttolerant techniques. This experiment was applied to a bistable processor of a reactor protection system.

• Journal of Korean Society for Quality Management
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• v.21 no.1
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• pp.78-95
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• 1993

The art of designing and analyzing fault-tolerant computers is surveyed with special emphasis on problems of analyzing the behavior of computers that have autonomous repair capability. The survey covers the following topics : (1) general issues in computer reliability, (2) fault-tolerance state relations and requirements, (3) computational hierarchy, (4) fault characteristics, (5) fault diagnosis, (6) fault-tolerance schemes for logic network and machines, (7) fault-coverage effects, and (8) fault-tree analysis of coverage. This paper does not include techniques for verifying nonredundant hardware or system software designs or for verifying the correctness of application programs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.11-20
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• 1998

Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• International Journal of Reliability and Applications
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• v.8 no.1
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• pp.53-66
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• 2007

This paper proposes a new non-homogeneous Poisson process software reliability growth model based on the coverage information. The new model incorporates the coverage information in the fault detection process by assuming that only the faults in the covered constructs are detectable. Since the coverage growth behavior depends on the testing strategy, the fault detection process is first modeled for the general testing strategy and then realized for the uniform testing. Finally the model for the uniform testing is empirically evaluated by applying it to real data sets.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.137-140
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• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.