• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.381-382
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• 2012

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.65-69
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• 2019

The cure properties of ethoxysilyl diglycidyl isocyanurate(Ethoxysilyl-DGIC) and ethylsilyl diglycidyl isocyanurate (Ethylsilyl-DGIC) epoxy resin systems with a phenol novolac hardener were investigated for anticipating fan out-wafer level package(FO-WLP) applications, comparing with ethoxysilyl diglycidyl ether of bisphenol-A(Ethoxysilyl-DGEBA) epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The isocyanurate type epoxy resin systems represented the higher cure conversion rates comparing with bisphenol-A type epoxy resin systems. The Ethoxysilyl-DGIC epoxy resin system showed the highest cure conversion rates than Ethylsilyl-DGIC and Ethoxysilyl-DGEBA epoxy resin systems. It can be figured out by kinetic parameter analysis that the highest conversion rates of Ethoxysilyl-DGIC epoxy resin system are caused by higher collision frequency factor. However, the cure conversion rate increases of the Ethylsilyl-DGEBA comparing with Ethoxysilyl-DGEBA are due to the lower activation energy of Ethylsilyl-DGIC. These higher cure conversion rates in the isocyanurate type epoxy resin systems could be explained by the improvements of reaction molecule movements according to the compact structure of isocyanurate epoxy resin.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.42-48
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• 2023

Recently, there has been an increasing demand for performance improvement and miniaturization in response to the growing variety of signals and power demands in many industries such as mobile, IoT, and automotive. As a result, there is a high demand for high-performance chips and advanced packaging technologies that can package such chips. In this context, the FOWLP process technology is a suitable technology, and this paper discusses the plasma application technologies that are being used and studied to improve the shortcomings of this process. The paper is divided into four parts, with an introduction and case studies for each of the plasma application technologies used in each part.

• Electrical & Electronic Materials
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• v.34 no.2
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• pp.4-11
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• 2021

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.53-58
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• 2018

Since the scaling-down of IC devices has been reached to their physical limitations, several innovative packaging technologies such as 3D packaging, embedded packaging, and fan-out wafer level packaging (FOWLP) are actively studied. In this study the fabrication of organic-inorganic dielectric material was evaluated for the use of multi-structured redistribution layers (RDL) in FOWLP. Compared to current organic dielectrics such as PI or PBO an organic-inorganic hybrid dielectric called polysilsesquioxane (PSSQ) can improve mechanical, thermal, and electrical stabilities. polysilsesquioxane has also an excellent advantage of simultaneous curing and patterning through UV exposure. The polysilsesquioxane samples were fabricated by spin-coating on 6-inch Si wafer followed by pre-baking and UV exposure. With the 10 minutes of UV exposure polysilsesquioxane was fully cured and showed $2{\mu}m$ line-pattern formation. And the dielectric constant of cured polysilsesquioxane dielectrics was ranged from 2.0 to 2.4. It has been demonstrated that polysilsesquioxane dielectric can be patterned and cured by UV exposure alone without a high temperature curing process.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.