• Journal of Technologic Dentistry
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• v.42 no.4
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• pp.313-320
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• 2020

Purpose: The purpose of this study is to compare and analyze the accuracy of single crowns based on the type of occlusal surface. Methods: A single crown wax pattern was fabricated in three types of occlusal surface. The prepared wax pattern was replicated with silicone, and stone was injected to create a stone model. The prepared specimens were scanned using a model scanner. Scans were classified into three groups, and each scan was performed six times to analyze the trueness and precision of a single crown. In addition, only the occlusal surface area was analyzed for trueness and precision. Data were analyzed using the Kruskal-Wallis H test, a nonparametric test (α=0.05). Results: With regard to the trueness value of the occlusal scan area, the no occlusal tooth attrition (NA) group showed the largest error of 3.5 ㎛, and the complete occlusal tooth attrition (CA) group showed the lowest value of 3.1 ㎛. The NA group had the greatest precision, and the medium occlusal tooth attrition (MA) group and CA group showed a low precision value of 3.2 ㎛; the difference between the groups was statistically significant (α=0.05). In the color difference map, the CA group showed a lower error than the NA group. Conclusion: The occlusal surface with severe attrition had excellent accuracy, but the accuracy of the group without attrition was low. There were significant differences between groups, but clinically acceptable values were shown.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.35 no.2
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• pp.33-40
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• 2023

Wave overtopping rate is one of the most important design parameters for coastal structures. In this study, the physical model tests for measuring the wave overtopping have been conducted with the foreshore slope in front of the seawall. The bottom seabed for the coastal road area was fabricated at the wave flume for two areas in the East sea areas. The wave overtopping rate was measured for various water depths and wave conditions in each coastal area. In particular, the impulsive wave conditions were compared with the previous research and the similar trends of wave overtopping was observed. It could be known that the effect of foreshore slope was significant and should be concerned for applying theses formula like EurOtop.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.9-15
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• 2007

In this paper, we present the design of Schottky diodes and voltage multiplier for UHF-band passive RFID applications. The Schottky diodes were fabricated using Titanium (Ti/Al/Ta/Al)-Silicon (n-type) junction in $0.35\;{\mu}m$ CMOS process. The Schottky diode having $4{\times}10{\times}10\;{\mu}m^{2}$ contact area showed a turn-on voltage of about 150 mV for the forward diode current of $20\;{\mu}A$. The breakdown voltage is about -9 V, which provides sufficient peak inverse voltage necessary for the voltage multiplier in the RFID tag chip. The effect of the size of Schottky diode on the turn-on voltage and the input impedance at 900 MHz was investigated using small-signal equivalent model. Also, the effect or qualify factor of the diode on the input voltage to the tag chip is examined, which indicates that high qualify factor Schottky diode is desirable to minimize loss. The fabricated voltage multiplier resulted in a output voltage of more than 1.3 V for the input RF signal of 200mV, which is suitable for long-range RFID applications.

• The Journal of Korean Academy of Prosthodontics
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• v.62 no.2
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• pp.157-164
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• 2024

A variety of digital technologies are being used throughout the entire implant treatment process of diagnosis, surgery, impression, design, and fabrication of prostheses. In this case, using a digital surgical guide, sinus floor elevation was performed without complications, and the implants were placed in the planned position. After the healing period for osseointegration, CAD-CAM (Computer-aided design-Computer-aided manufacturing) customized abutments and provisional prostheses were delivered. While using the provisional prosthesis, occlusal change was observed. To transfer the intermaxillary relationship and abutment position that reflect occlusal change and axial displacement, double scanning and abutment-level digital impressions were taken. Abutment superimposition was used to capture the subgingival margin without gingival retraction. Then, the definitive prosthesis was designed and fabricated with digital system. We report a case applying digital system, to achieve the predictable result as well as the efficient treatment process from implant surgery to fabricating prosthesis in the posterior area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).