• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.86-94
• /
• 2007

The NoC (network-on-chip) approach is a promising solution to the increasing complexity of on-chip communication problems because of its high scalability. But, NoC applications generally consume a lot of power, because they require a large design space to accommodate many parallel IPs and network communication channels. It is not easy to analyze the power consumption of NoC applications with conventional simulation methods using simple power models. In addition, there are also many limitations in using sophisticated simulation models because they require long execution time and large efforts. In this paper, we apply a cycle-accurate energy measurement technique and tool to the FPGA prototypes, which are generally used to verify the correctness of SoC designs, as a practical indication of the power consumption of real NoC applications. An NoC-based JPEG encoder implementation is used as a case study to demonstrate the effectiveness of our approach.

• Journal of Power Electronics
• /
• v.15 no.3
• /
• pp.644-651
• /
• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.2944-2946
• /
• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.10a
• /
• pp.76-78
• /
• 2015

시스템 자체를 에뮬레이션 하는 Virtual Platform은 임베디드 시스템 개발 프로세스 과정 중 하나인 소프트웨어 개발의 시점을 앞당길 수 있어 Time-To-Market을 줄일 수 있다. 본 논문에서는 Virtual Platform에 리눅스를 포팅하고 벤치마크 프로그램을 수행하여 성능을 측정하였다. 또한 이를 임베디드 시스템의 실제 개발단계에서 사용되는 Prototype Machine과 완성된 시제품에 각각 매칭 될 수 있는 FPGA 와 PC의 성능과 비교함으로써 Open Source Virtual Platform의 대표 주자인 QEMU의 효용성을 연구하였다. 실험 결과, 전체적인 성능은 PC가 FPGA보다 약 5.27배, FPGA가 Virtual Platform보다 5.38배, PC가 Virtual Platform보다 약 28.36배 더 좋은 성능을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.7
• /
• pp.50-57
• /
• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2019.05a
• /
• pp.251-253
• /
• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.2
• /
• pp.293-298
• /
• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of Advanced Navigation Technology
• /
• v.18 no.6
• /
• pp.541-545
• /
• 2014

Rec. ITU-R M.1842-1 is international recommendation for VHF band communication guideline in maritime mobile service RR Appendix 18 channels. In this paper, we simulate 28.8 kbps VHF ${\pi}$/4-DQPSK digital baseband modem compatible with the recommendation, then it is designed and implemented with FPGA. Cazac sequence is used as a preamble since packet format is not defined untill now in the recommendation. Baseband modem is designed by VHDL language and implemented on NEXYS4 development platform having Atrix7 FPGA chip from Xilinx. For wireless communication test of total prototype system, ADC/DAC board is implemented and EV9730 RF module is utilized. From the experimental results, implemented FPGA modem shows spectral bandwidth of 25 kHz and successful data exchanges between tx and rx communication platform.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• ETRI Journal
• /
• v.39 no.4
• /
• pp.525-534
• /
• 2017

A hardware-acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software-defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network-intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA-10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.