• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.44-52
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• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.148-151
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• 2000

In recent years, security is essential factor of our safe network community. Therefore, data encryption/ decryption technology is improving more and more. Elliptic Curve Cryptosystem proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits lot the same security, there is a net reduction in cost, size, and time. In this paper, we design high speed underlying field arithmetic processor for elliptic curve cryptosystem. The targeting device is VIRTEX V1000FG680 and verified by Xilinx simulator.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of Broadcast Engineering
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• v.8 no.4
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• pp.452-464
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• 2003

In this paper, a multi-view 3D video processor was designed and implemented with several FPGAs for real-time applications. The 3D video processor receives 2D images from cameras (up to 16 cameras) and converts then to 3D video format for space-multiplexed 3D display. It can cope with various arrangements of 3D camera systems (or pixel arrays) and resolutions of 3D display. Tn order to verify the functions of 3D video Processor. some evaluation-board were made with five FPGAs.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.25-29
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• 2008

The CORBA that supports FPGA has not been used generally and it is difficult to implement and to develop the CORBA for FPGA. In this paper we propose the way to design FPGA to support a CORBA component. For FPGA to support the CORBA component, embedded processor provided by FPGA and PCI based CORBA is utilized. The PCI based CORBA is for improving data transfer throughput. This paper will be organized as follows. In Chapter I, existing research trend and background are presented for why we propose design of FPGA that support the CORBA component. In Chapter II, FPGA design for supporting CORBA components is proposed and described in detail. In Chapter III, simple experiment is tested to confirm the proposed FPGA design. Finally session 4 is conclusion of this paper.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.120.5-120
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• 2002

1. Introduction 2. Property of FPGA 3. Evolvable Hardware (EHW) 4. Genetic Algorithm Processor (GAP) 5. State Machine 6. Conclusion

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.213-218
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• 2008

This paper describes hardware-based high speed multimedia data reassembly processor for remote multimedia Set-Top-Box(MSTB) of interactive satellite multimedia communication system. The conventional multimedia data reassembly scheme is based on software processing of MSTB. As increasing of transmission rate for multimedia data services, the CPU load of remote MSTB is increased and reassembly performance of MSTB is limited. To provide high speed multimedia data service to end user, we proposed hardware based high speed multimedia data reassembly processor. It is implemented by using an FPGA, a PCI interface chip, and RAMs. And it is integrated in MSTB and tested. It has been confirmed to meet required all functions and processing rate up to 116Mbps.