Browse > Article

Design of Video Processor for Multi-View 3D Display  

성준호 (삼성전자(주) DM총괄)
하태현 (삼성전자(주) DM총괄)
김성식 (삼성전자(주) DM총괄)
이성주 (삼성전자(주) DM총괄)
김재석 (연세대학교 전기전자공학과)
Publication Information
Journal of Broadcast Engineering / v.8, no.4, 2003 , pp. 452-464 More about this Journal
Abstract
In this paper, a multi-view 3D video processor was designed and implemented with several FPGAs for real-time applications. The 3D video processor receives 2D images from cameras (up to 16 cameras) and converts then to 3D video format for space-multiplexed 3D display. It can cope with various arrangements of 3D camera systems (or pixel arrays) and resolutions of 3D display. Tn order to verify the functions of 3D video Processor. some evaluation-board were made with five FPGAs.
Keywords
Citations & Related Records
연도 인용수 순위
  • Reference
1 G. de Haan, and E. B. Bellers, 'Deinterlacing - An Overview', Proceeding of the IEEE, vol. 86, No. 9, pp. 1839-1857, 1998
2 A. Puri, R. V. Kollarits and B. G. Haskell, 'Basics of stereoscopic video, new compression results with MPEG-2 and a proposal for MPEG-4', Signal Processing : Image Communication, vol. 10, pp.201-234, 1997
3 C. van Berkel, D. W. Parker and A. R. Franklin, 'Multi-view 3D LCD', Proc. SPIE, vol. 2653, pp. 32-39, 1996
4 M. Okui, F. Okano and I. Yuyama, "A study on scanning methods for a field-sequential stereoscopic display",IEEE Trans. Circuit and Systems for Video Technology, vol. 10, no. 2, pp. 244-253, 2000
5 I. Sexton and P. Surman, 'Stereoscopic and autostereoscopic display systems', IEEE Signal Processing Magazine, vol. 16, no. 3, pp. 85-99, 1999