• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.1-8
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• 2023

This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.21-28
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• 2024

This paper presents the design and implementation of ML-DSA, a next-generation post-quantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the ML-DSA algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU104 FPGA. Finally, the video and document were saved and processing with Python code in the PYNQ framework, and the video data’s digital signature generation and verification were accelerated using ML-DSA hardware accelerator implemented on the FPGA.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.69-77
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• 2024

This paper presents that the SLH-DSA, a next-generation post-quantum cryptography, was designed as a hardware accelerator using High-Level Synthesis (HLS), implemented in the FPGA, and the performance analysis results show its superiority. The optimization design of the SLH-DSA was carried out using HLS technology, and the hardware accelerator of the digital signature and verification system was designed. The implementation and simulation were carried out using the ZYNQ UltraScale+ MPSoC ZCU104 FPGA. Finally, as a result of comparing the performance of the SLH-DSA hardware accelerator implemented in the FPGA with the CPU-based implementation, the execution time of the algorithm improved by about 596%, demonstrating the effectiveness of hardware acceleration.

• Annual Conference of KIPS
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• 2019.05a
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• pp.479-481
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• 2019

본 연구에서는 이미지를 분류하는 인공 신경망 가속기를 최적화했고, 이를 구현하여 기존 인공 신경망 가속기와 성능을 비교 분석했다. FPGA(Field Programmable Fate Array) 보드를 이용하여 가속기를 구현했으며, 해당 보드의 내부 메모리인 BRAM 을 FIFO(First In First Out)구조로 설계하여 메모리 시스템을 구현했다. Approximate computing 기법을 효율적으로 적용하기 위해 FWL(Fractional Word Length)최적점을 분석했고, 이를 기반으로 인공 신경망 가속기의 부동 소수점 연산을 고정 소수점 연산으로 변환했다. 구현된 인공 신경망 가속기는 기존의 인공 신경망에 비해, 약 7.4%더 효율적인 전력소모량을 보였다.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.46-51
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• 2024

Deep Reinforcement Learning (DRL) has demonstrated human-level performance in sequential decision-making tasks and enables edge devices to adapt autonomously to unknown environments. However, implementing DRL adaptation remains challenging due to its massive data interactions and extensive DNN computations. Existing FPGA-based DRL accelerators focus solely on computation acceleration, leading to prolonged adaptation times. This paper proposes an energy-efficient FPGA accelerator tailored for fast online DRL adaptation, leveraging three key innovations: 1) A Heterogeneous Replay Buffer (HRB) that reduces training iterations by up to 90%, 2) Mixed-Precision Selective Re-Training (MP-SELRET) that decreases computations by 12% while replacing 27.2% of 32-bit floating-point operations with 16-bit fixed-point operations, 3) A Mixed-Precision Heterogeneous Architecture (MPHA) that maximizes resource utilization and boosts throughput by 39.8%. The proposed accelerator significantly enhances the efficiency and speed of DRL adaptation, addressing the limitations of traditional scratch trainingmethods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1279-1286
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• 2021

The electrocardiogram (ECG) signal is a good indicator for early diagnosis of heart abnormalities. The ECG signal has a different reference normal signal for each person. And it requires lots of data to diagnosis. In this paper, we propose an adaptive OpenCL-based FPGA-GPU hybrid-layer platform to efficiently accelerate ECG signal diagnosis. As a result of diagnosing 19870 number of ECG signals of MIT-BIH arrhythmia database on the platform, the FPGA accelerator takes 1.15s, that the execution time was reduced by 89.94% and the power consumption was reduced by 84.0% compared to the software execution. The GPU accelerator takes 1.87s, that the execution time was reduced by 83.56% and the power consumption was reduced by 62.3% compared to the software execution. Although the proposed FPGA-GPU hybrid platform has a slower diagnostic speed than the FPGA accelerator, it can operate a flexible algorithm according to the situation by using the GPU.

• Annual Conference of KIPS
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• 2021.11a
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• pp.313-314
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• 2021

최근 개인 정보 보호를 위해 주목 받고 있는 동형암호 알고리즘은 암호화된 상태로 덧셈과 곱셈 연산이 가능하여, 연산을 위한 복호화 과정 없이 데이터에 대한 가공이 가능하다. 따라서 이러한 동형암호 알고리즘이 개인 정보 보호를 위한 방법으로 떠오르고 있으며, 특히 완전동형암호 알고리즘의 경우 덧셈과 곱셈 연산을 모두 지원하며, 유효 연산 횟수에도 제한이 없어 응용 분야에서 널리 활용될 것으로 예상된다. 그러나, 완전동형암호 알고리즘의 경우 암호문의 크기가 평문대비 크게 증가하고, 다항식으로 구성된 암호문의 덧셈 및 곱셈 연산도 복잡하여 이에 대한 가속이 필요한 실정이다. 이에 FPGA 기반의 동형암호 가속기 개발이 많이 연구되고 있으며, 이를 통해 동형암호 연산의 특징을 이해하고 가속기 연구 동향을 알아보려 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1667-1674
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• 2018

Recently, speeding up real time calculation using the specialized hardware accelerator is often used in the various engineering and science area, and the accelerators are required to include PCI express interconnection between FPGA and a host computer. The implementation of the high speed PCIe for the multi-giga bytes per second transmission is one of the most difficult issue in the development of the accelerators. There are several commercialized IP solutions and research results in the literature, but these solutions are required extra cost and design period to analyze the detailed implementation method. For the hardware accelerator on Xilinx FPGA, utilizing Xilinx's XDMA PCIe IP, which is provided without extra charge, can be the best solution in terms of the development period and cost. Consequently, this paper presents the evaluation system on Zynq-7000 FPGA and Windows 10 host computer, and analyze the performance of the PCIe IP with various configuration parameters.