• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.288-295
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• 2010

Multi-level inverters have drawn much of attention in recent years because it can meet the demand of high power applications and good power quality associated with reduced harmonic distortion. As the number of voltage level increases, field programmable gate arrays (FPGAs) are suitable for the implementation of multi-level modulation algorithm. This paper proposes the implementation method for generating PWM pulses at the three phase diode clamped five-level inverter using FPGA. The strategy for communicating stably the data of three-phase reference voltages between the DSP and FPGA is suggested. The techniques for generating PWM signals based on a multi-carrier modulation method are carried out through the experiments with 32-bit DSP and Cyclone-III FPGA.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.4
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• pp.339-345
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• 2007

This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.403-406
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• 2001

본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• Journal of Digital Contents Society
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• v.10 no.4
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• pp.633-637
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• 2009

In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.223-225
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• 2007

본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP (Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시간을 감소시킬 수 있다. 이는 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반의 전류 제어기의 성능은 실험을 통해 검증되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.464-466
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• 2019

Controllers used in nuclear power plants require high reliability. A controller including a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (referred to hereinafter as FPGA) has been applied to many Nuclear Power Plants (NPP) in the past, including the APR1400 (Advanced Power Reactor 1400), a Korean digital nuclear power plant. Initially, the FPGA was considered as a general IC (Integrated Circuit) and verified only by device verification and performance testing. In the 1990s, research on FPGA verification began, and until the FPGA became a chip, it was regarded as software and the software Verification and Validation (V&V) using IEEE 1012-2004 was implemented. Currently, IEC 62566, which is a European standard, has been applied for a lot of verification. This method has been evaluated as the most sensible method to date. This is because the method of verifying the characteristics of SoC (System on Chip), which has been a problem in the existing verification method, is sufficiently applied. However, IEC 62566 is a European standard that has not yet been adopted in the United States and maintains the application of IEEE 1012 for FPGA. IEEE 1012-2004 or IEC 62566 is a technical standard. In practice, various methods are applied to meet technical standards. In this paper, we describe the procedure and important points of verification method of Nuclear Safety Class FPGA applying SoC verification method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.389-390
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.723-724
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• 2013

• Journal of KIISE
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• v.43 no.5
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• pp.569-578
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• 2016

The PLC (Programmable Logic Controller) has been widely used for the development of digital control system of nuclear power plant. The PLC has high maintenance costs and increasing complexity, hence, FPGA (Field Programmable Gate Array) based digital control system has been considered as an alternative. However, the development of FPGA based digital control system is a challenge for PLC engineers because they are required to learn about new language to develop FPGA and knowledge and know-how acquired in the development of PLC is not transferable. In this study, we proposed and implemented an automatic translation tool for translation of FBD (Function Block Diagram), a programming language of PLC software, into VHDL (VHSIC Hardware Description Language). Automatically translating the FBD to VHDL using this tool allows PLC engineers to develop FPGA without any knowledge of the hardware description language.