• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.686-689
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• 2002

This paper proposes a weighted least-squares(WLS) method for designing variable one-dimensional (1-D) FIR digital filters with simultaneously variable magnitude and variable non-integer phase-delay responses. First, the coefficients of a variable FIR filter are represented as the two-dimensional (2-D) polynomials of a pair of spectral parameters: one is for tuning the magnitude response, and the other is for varying its non-integer phase-delay response. Then the optimal coefficients of the 2-D polynomials are found by minimizing the total weighted squared error of the variable frequency response. Finally, we show that the resulting variable FIR filter can be implemented in a parallel form, which is suitable for high-speed signal processing.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.11
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• pp.1053-1059
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• 2007

This paper presents a target sate estimator(TSE) with low pass filter for improving the gun driving command. The ballistic computer uses target information such as predicted range, velocity, acceleration of a target to generate the gun command. We adopt the finite impulse response(FIR) filter as our TSE to shorten calculation time for the driving command and due to its inherent stability property. We also introduce a post-processing filter to reduce the high frequency components in the output signal of a TSE which may cause instability of gun driving. The first order low pass filter has been designed based on $H{\infty}$ criteria considering the noise characteristics. To show the validity of the present scheme, simulation results are given for the overall gun driving system including aircraft target information.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• Journal of Biomedical Engineering Research
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• v.16 no.1
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• pp.49-56
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• 1995

This paper is a study on the design of adptive filter for QRS complex detection. We propose a simple adaptive algorithm to increase capability of noise cancelation in QRS complex detection with two stage adaptive filter. At the first stage, background noise is removed and at the next stage, only spectrum of QRS complex components is passed. Two adaptive filters can afford to keep track of the changes of both noise and QRS complex. Each adaptive filter consists of prediction error filter and FIR filter. The impulse response of FIR filter uses coefficients of prediction error filter. The detection rates for 105 and 108 of MIT/BIH data base were 99.3% and 97.4% respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.3
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• pp.612-621
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• 1996

In this paper, we propose the low sidelobe digital FIR doppler filter bank synthesis algorithm through the Gradient Descent method and it can be practially appliable to coherent pulse doppler radar signal processing. This algorithm shows the appropriate calculation of tap coefficients or zeros for FIR transversal fiter which has been employed in radar signal processor. The span of the filters in the filter bank be selected at the desired position the designer want to locate, and the lower sidelobe level that has equal ripple property is achieved than one for which the conventional weithtedwindow is used. Especially, when we implemented filter zeros as design parameters it is possible to make null filter gain at zero frequency intensionally that would be very efficient for the eliminatio of ground clutter. For the example of 10 tap filter synthesis, when filter coefficients or zeros are selected as design parameters the corresponding sidelobelevel is reducedto -70db or -100db respectively and it has good convergent characteristics to the desired sidelobe reference value. The accuracy ofapproach to the reference value and the speed of convergence that show the performance measure of this algorithm are tuned out with some superiority and the fact that the bandwidth of filter appears small with respect to one which is made by conventional weighted window method is convinced. Since the filter which is synthesized by this algorithm can remove the clutter without loss of target signal it strongly contributes performance improvement with which detection capability would be concerned.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.2
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• pp.59-66
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• 2008

In this study, Software Defined Radio (SDR) technology-based digital filterbank architecture applicable to a multiple-channel processing system such as a wireless mobile communication system using Code Division Multiple Access (CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response (FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter (BPF) to reconfigure another system. The feasibility of the algorithm is verified by computer simulation and by implementing a multiple-channel signal generator that is reconfigurable to other system profiles, including those of a Wideband Code Division Multiple Access (WCDMA) system and a CDMA system.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.511-512
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• 2006

Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.234-237
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• 2003

The accuracy of channel estimation significantly affects the performance of coherent OFDM receiver. It is desirable to employ a good channel estimator while requiring low implementation complexity. In this paper, we propose a channel estimator that employs a simple two-dimensional (2-D) moving average (MA) filter as the channel estimation filter. The optimum tap size of the 2-D MA FIR filter is analytically designed in the time and frequency domain in association with the channel condition and pilot signal to interference power ratio. The analytic results can be applied to the design of adaptive channel estimator. Finally, the performance of the proposed channel estimator is verified by computer simulation.