• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.577-584
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• 2005

Optimal methods for designing multiplierless minimal complexity FIR filters with cascaded prefilter-equalizer structures are proposed for narrowband communication systems. Assuming that an FIR filter consists of a cyclotomic polynomial(CP) prefilter and an interpolated second order polynomial(ISOP) equalizer, in the proposed method the prefilter and equalizer are simultaneously designed using mixed integer linear programming(MILP). The resulting filter is a cascaded filter with minimal complexity. Design examples demonstrate that the proposed methods produce a more computationally efficient cascaded prefilter-equalizer than other existing filters.

• International journal of advanced smart convergence
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• v.4 no.2
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• pp.138-144
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• 2015

Digital filters are extensively used in the world of communication. In order to design a digital finite impulse response (FIR) filter that satisfies all the required conditions is challenging. In this paper, design techniques of digital low pass FIR filters using Rectangular window method, Hamming window, Hanning window, and Optimal Parks McClellan method are presented. The stability, number of components required and filter coefficients are demonstrated for different design techniques. It is demonstrated that filter design using hamming window is comparatively better than rectangular and hanning window though the components required for all of the windowing technique are same, hamming shows higher stability. The stability is shown with the help of magnitude and phase spectrum of each window. Simulation is carried out using MATLAB and comparisons are made entirely based on the output of the simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.35-40
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• 2006

In this paper, a current-mode analog variable finite-impulse-response (FIR) filter with variable tap coefficient circuits is proposed for frequency selective wireless personal area network(WPAN) system or terminals. From the circuit simulation the operation of the 7-tap FIR filter is confirmed. The 0.0625-step tap coefficient circuit is designed and fabricated with $0.8[{\mu}m]$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to frequency selective WPAN system or frequency selective wireless communication terminals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.1
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• pp.38-41
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• 1985

The hybrid design which is to take IIR filter of the first stage as a second order pole-zero model and minimize the filter length of the of the FIR filter of the following stage is presented. The outcome of the simulation showed us that the the filter length in the hybrid filters was remarkably decreased compared to that of the hybrid filters which take the IIR filter as a all-pole model. Although the hybrid filters couldn't obtain the exact linear phase. it was superior to the IIR filters in passband and stopband.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.219-222
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• 2009

An efficient interpolation FIR filter structure for high-density and low-power electronic devices is proposed. The proposed structure is based on polyphase decomposition property and look-up table method. By computer-aided design simulations, it is shown that the use of the proposed method can result in reduction in the number of gates by 54% and can reduce power consumption by 9%.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Journal of Biomedical Engineering Research
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• v.10 no.2
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• pp.83-88
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• 1989

This paper is a study on the design of adptive filter for QRS complex detection. We propose a simple adaptive algorithm to increase capability of noise cancelation in QRS complex detection with two stage adaptive filter. At the first stage, background noise is removed and at the next stage, only spectrum of QRS complex components is passed. Two adaptive filters can afford to keep track of the changes of both noise and QRS complex. Each adaptive filter consists of prediction error filter and FIR filter The impulse response of FIR filter uses coefficients of prediction error filter. The detection rates for 105 and 108 of MIT/BIH data base were 99.3% and 97.4% respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.452-456
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• 2010

Multiplication is a fundamental arithmetic operation in many digital signal processing (DSP) and communication algorithms. The group CSD (GCSD) multiplier was recently proposed based on the variation of canonical signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In this paper, it is shown that, by exploiting the characteristics of the filter coefficients, GCSD multipliers can be used for the efficient implementation of time-multiplexed FIR filters.