• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.193-196
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• 1998

지금까지 바이노럴 필터 설계 방법들의 대부분은 linear frequency scale을 이용한 것이지만, 사람의 귀는 non-linear frequency scale을 가지며 critical band에 의한 청각정보를 인지한다. 따라서, 이와 같은 특징을 이용하여 좀 더 효율적으로 바이노럴 필터를 설계할 수 있다. 본 논문에서는 frequency warping을 이용해 non-linear frequency resolution을 갖는 바이노럴 필터를 계산한다. 또한, 종래의 설계방법에 의한 필터와 warped FIR 구조를 갖는 바이노럴 필터와의 비교청취를 통해 성능의 비교 평가를 수행 한다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.79-81
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• 1987

In this paper we propose a fast adaptive least squares algorithm for linear phase FIR filters. The algorithm requires 10m multiplications per data point where m is the filter order. Both linear phase cases with constant phase delay and constant group delay are examined. Simulation results demonstrate that the proeposed algorithm is superior to the LMS gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm.

• The Journal of the Korea Contents Association
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• v.5 no.6
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• pp.74-86
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• 2005

In this paper, we proposed an algorithm for the approximation of high order FIR filters by low order IIR filters to efficient implementing two channel 3-D surround sound systems using Head-related transfer functions(HRTFs). The algorithm is based on a concept of the balanced model reduction. The binaural sounds using the approximated HRTFs are reproduced by headphone, and serves as a cue of sound image localization. HRTFs of dummy-head are approximated from 512-order FIR filters by 32-order IIR filters and compare with each other. .Experiment of sound image are carried out for 10 participants. We perform the experiment based on computer simulation and hardware experiment with TMS320C32. The results of the experiments show that the localization using the approximated HRTFs is the same accuracy as the case of FIR filters that simulate the HRTFs.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• The Journal of the Convergence on Culture Technology
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• v.6 no.3
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• pp.427-430
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• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.282-283
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• 2008

본 논문에서는 효율적인 2-D FIR 노치필터 디자인 방법을 제안한다. 주파수대역에서 bandstop 필터 형태를 보이는 Zolotarev 다항식을 Chebyshev 다항식으로 확장 적용한 1-D dc 노치필터의 설계 방법, 주파수 이동, 그리고 임펄스 응답의 2-D 선형 컴볼루션을 이용하여 효율적인 2-D FIR 노치 필터설계 방법을 제안한다. 시뮬레이션을 통하여, 설계된 2-D 노치필터 특성을 검증한다.