• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.266-268
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• 2013

In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is $10^{20}atoms/cm^3$. The simulation results show that I-V characteristics of JLT change due to the variation of channel doping concentration.

• Journal of Sensor Science and Technology
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• v.20 no.4
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• pp.260-265
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• 2011

The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.195.2-195.2
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• 2013

플라즈마 중합 증착기술을 이용하여 ppMMA (plasma polymerized methyl methacrylate) 및 ppS (plasma polymerized styrene) 박막을 제작하고, ppMMA를 게이트 절연층, polymer electret인 ppS를 메모리층으로 한 전계효과트랜지스터 기반 유기 메모리 소자를 제작하였다. 메모리층인 ppS의 두께를 각각 30, 60, 90 nm로 달리한 유기 메모리 소자가 C-V 및 I-V 특성에서 나타내는 히스테리시스 현상을 분석하여 메모리 특성을 평가했으며, 메모리층의 두께 변화에 따른 유기 메모리 소자의 성능을 비교분석하였다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.136-141
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• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.26.2-26.2
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• 2009

A simple route of externalmechanical force is presented for enhancing the electrical properties ofpolymer nanocomposite consisted of nanowires. By dispersing ZnO nanowires inpolymer solution and drop casting on substrates, nanocomposite transistorscontaining ZnO nanowires are successfully fabricated. Even though the ZnOnanowires density is properly controlled for device fabrication, as-cast devicedoesn't show any detectablecurrents, because nanowires are separated far from each other with theinsulating polymer matrix intervening between them. Compared to the devicepressed at 300 kPa, the device pressed at 600 kPa currents increased by 50times showing the linear behavior against drain voltage and exhibits promisingelectrical properties, which operates in the depletion mode with highermobility and on-current. Such an improved device performance would be realizedby the contacts improvement and the increase of the number of electrical pathinduced by external force. This approach provides a viable solution for seriouscontact resistance problem of nanocomposite materials and promises for futuremanufacturing of high-performance devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Applied Science and Convergence Technology
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• v.23 no.3
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• pp.134-138
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• 2014

One-dimensional nanostructures such as nanowires have been extensively investigated as a promising type of material for applications of nanoscale technology. The fabrication of single-nanowire devices are consequently important and interesting. This study introduced a feasible method for growing CuO nanowires on Cu foils. The nanowires had diameters of 10~150 nm and lengths of more than $7{\mu}m$ and were grown by means of thermal oxidation in a vacuum. They were entirely and uniformly grown over the Cu foil surfaces and could be extracted and dispersed in an ethanol solution for further purposes. In addition, a simple fabrication method for realizing device functionality from a single CuO nanowire was reported. Fabricated devices were carefully checked by field-emission scanning electron microscopy (SEM). The probability of the realization of a single-CuO-nanowire device relative to that of all other types was estimated to be around 25%. Finally, the I-V characteristics of the devices were analyzed.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.1
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.