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http://dx.doi.org/10.5369/JSST.2011.20.4.260

Magnetic Sensitivity Improvement of Silicon Vertical Hall Device  

Ryu, Ji-Goo (Department of Electronics Eng., Pukyong National University)
Kim, Nam-Ho (Department of Control & Instrumentation Eng., Pukyong National University)
Chung, Su-Tae (Department of Electronics Eng., Pukyong National University)
Publication Information
Journal of Sensor Science and Technology / v.20, no.4, 2011 , pp. 260-265 More about this Journal
Abstract
The silicon vertical hall devices are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$, interface and n-epi layer without $n^+$buried layer to improve the sensitivity and influence of interface effects. Experimental samples are a sensor type I with and type H without p+isolation dam adjacent to the center current electrode. The experimental results for both type show a more high current-related sensitivity than the former's vertical hall devices. The sensitivity of type H and type I are about 150 V/AT and 340 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.
Keywords
Vertical Hall Device; $n^+$buried Layer; Thin p-layer; $p^+$ Isolation Dam;
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Times Cited By KSCI : 2  (Citation Analysis)
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