• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.191-194
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• 1999

Switching behaviour of the ferroelectric thin film and device characteristics of the MFSFET (Metal-Ferroelectric-Semiconductor FET) are simulated with taking into account the accumulation of oxygen vacancies near interface between the ferroelectric thin film and the bottom electrode caused by the progress of fatigue. We show net switching current decreases due fatigue in the switching model. It indicates that oxygen vacancy strongly suppresses polarization reversal. The difference of saturation drain current of the device before fatigue is shown by the dual threshold voltages in I$_{D}$-V$_{D}$ curve as 6㎃/$\textrm{cm}^2$ and decreases as much as 50% after fatigue. Our simulation model is expected to play an important role in estimation of the behavior of MFSFET device with various ferroelectric thin films.lms.

• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.5
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• pp.787-794
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• 2001

In this paper, the development of large-signal model extractor for GaAs FET device through the Monolithic Microwave integrated Circuit(MMIC) is presented. The measurement program controlled by personal computer is developed for the processing of an amount of measured data, and the de-embedding algorithm is added to the program for voltage dropping as attached series resistance on measurement system. The small-signal model parameters are typically consisted of 7 elements that are considered as complexity of large-signal model and its the accuracy of the small-signal model is verified through comparing with measured data as varied bias point. The fitting function model, one of the empirical model, is used for quick simulation. In the process of large-signal model parameter extraction, one-dimensional optimization method is proposed and optimized parameters are extracted. This study can reduce the modeling and measuring time and can secure a suitable model for circuit.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.1-12
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• 2001

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.12-17
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• 2004

The body-tied FinFETs (bulk FinFETs) implemented on bulk Si substrate were characterized through 3-dimensional device simulation. By controlling the doping profile along the vertical fin body, the bulk FinFETs can be scaled down to sub-30 nm. Device characteristics with the body shape were also shown. At a contact resistivity of $1{\times}10^{-7}\;{\Omega}\;cm^2$, the device with side metal contact of fin source/drain showed higher drain current by about two. The C-V results were also shown for the first time.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.260-263
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• 2013

A semiconducting single-walled carbon nanotube (SWCNT) field-effect transistor (FET) in a top-gate model was constructed. The effect of different high-${\kappa}$ dielectric materials ($Al_2O_3$, $HfO_2$ and HfSiON) and various temperatures with a wide range from 50K to 500K on the performance of such nominal device were investigated. Several key device parameters including the on/off ratio of the current, transconductance ($g_m$), subthreshold swing, and carrier mobility were used to evaluate the device performance. The simulated results fit well with the experiment results previously published.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.8-17
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• 1992

In this paper a push-push oscillator using DR (dielectric resonator) at K-band is designed and constructed. Two identical oscillators are arranged in a push-push configuration that has the frequency of oscillator that is twice frequency each oscillator. A dielectric resonator is placed at the input of an active two-port device(FET) yielding a stable frequency source. The oscillators realized with this technique exhibit excellent spectral purity and cancellation of fundamental frequency.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.12a
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• pp.110-111
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• 2007