• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.1
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• pp.47-52
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• 2007

Organic field-effect transistors (OFETS) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with varying channel length. The CuPc FET device was made a top-contact type and the channel length was a $100\;{\mu}m,\;50\;{\mu}m,\;40\;{\mu}m,\;and\;30\;{\mu}m$ and the channel width was a fixed at 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with varying channel length (L) and we calculated the effective mobility. Also, we measured a capacitance-voltage (C-V) by applied bias voltage with varying frequency at 43, 100, 1000 Hz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1018-1022
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.3
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• pp.11-17
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• 1978

A medium scale integrated circuit, BCD to seven segment decoder/driver is designed and fabricated by employing P-channel metal-oxide-semiconductor technology. The device configuration is specifically designed for a common cathode seven segment LED display unit. The decoder logic is composed of two serially connected read-only-memory matrices and the LED drivers are implemented with wide channel FET's. The fabricated integrated circuit performed successfully with a supply voltage between -7 Volt and -26 Volt and the non-uniformity of the LED segment current is about 10%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.197-197
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• 2012

Device 제작에 사용된 graphene은 일반적인 lithography 공정에서 resist residue에 의한 오염을 피할 수 없으며 이로 인하여 graphene의 pristine한 성질을 잃어버린다. 본 연구에서는 graphene을 저밀도의 argon inductively coupled plasma (Ar-ICP)를 통해 처리함으로서 graphene based back-gated field effect transistor (G-FET)의 특성변화를 유도한 결과에 대해서 보고한다. Argon capacitively coupled plasma (Ar-CCP)은 에 노출된 graphene은 강한 ion bombardment energy로 인하여 쉽게 planar C-C ${\pi}$ bonding (bonding energy: 2.7 eV)이 breaking되어 graphene의 defect이 발생되었다. 하지만 우리의 경우 저밀도의 Ar-ICP가 적용될 때 graphene의 defect이 제한되며 이와 동시에 contamination 만을 제거할 수 있었다. 소자의 전기적 측정 (Gsd-Vbg)을 통하여 contamination으로 인하여 p-doping된 graphene은 pristine 상태로 회복되었으며 mobility도 회복됨이 확인되었다. Ar-ICP를 이용한 graphene cleaning 방법은 저온공정, 대면적 공정, 고속공정을 모두 만족시키며 thermal annealing, electrical current annealing을 대체하여 graphene 기반 소자를 생산함에 있어 쉽고 빠르게 적용할 수 있는 강점이 있다.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.53-55
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• 2005

The surface potential variations are measured, according to the enhanced measuring speed and voltage sensitivity, using an active device, such as a field effect transistor $(FET)^{1-3}$. In this study, the surface potential was mapped in the patterned $SiO_2$ medium at room temperature. An improved FET-tip cantilever, which has a source, a drain, and an n- channel, was used in this study. The potential images were analyzed both in the contact mode and the non-contact mode, using only a pre-amplifier system instead of a lock-in the amplifier.

• Proceeding of EDISON Challenge
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• 2015.03a
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• pp.357-364
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• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.40-42
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• 2011

An organic field-effect transistor (OFET) was fabricated using a copper phthalocyanine (CuPc) as the active layer on the silicon substrate. The CuPc FET device was configured as a top-contact type. The substrate temperature was room temperature. The CuPc thickness was 40 nm, and the channel length and channel width were 100 ${\mu}m$ 3 mm, respectively. Typical current-voltage (I-V) characteristics of the CuPc FET were observed and subsequently compared to the UV/ozone treatment on substrate surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.494-495
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.