• 한국정보전자통신기술학회논문지
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• 제9권4호
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• pp.419-427
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• 2016

본 논문에서는 저면적 64bit MTP IP를 설계하였다. 저면적 설계기술로는 MTP cell의 inhibit voltage를 기존의 VPP/3과 VNN/3 전압 대신 모두 0V를 사용하므로 VPPL(=VPP/3) regulator 회로와 VNNL(VNN/3) charge pump 회로를 제거하였다. 그리고 external pad를 이용하여 VPP program voltage를 forcing하므로 VPP charge pump 회로를 제거하였다. 또한 VNN charge pump는 VPP 전압을 이용하여 1-stage negative charge pump 회로로 pumping해서 -VPP의 전압을 공급하도록 설계를 하였다. 설계된 64bit MTP IP size는 $377.585{\mu}m{\times}328.265{\mu}m$(=0.124mm2)이며, DC-DC converter관련 layout size는 기존의 회로 대비 76.4%를 줄였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Journal of Power Electronics
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• 제17권2호
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.997_998
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• 2009

Nowadays DC-DC converter has been used widely in electronic production. It has a high requirement in wide input voltage, load variations, stability, providing a fast transient response and the most important thing is that it can be applied easily and efficiently. However, it is not easy to be controlled because of nonlinear system. This study introduces a fuzzy linear control design method for nonlinear systems with optimal $H^{\infty}$ robustness performance. First, the Takagi and Sugeno fuzzy linear model is employed to approximate a nonlinear system. Next, based on the fuzzy linear model, a fuzzy controller is developed to stabilize the nonlinear system, and at the same time the effect of external disturbance on control performance is attenuated to a minimum level. Thus based on the fuzzy linear model, ��$H^{\infty}$ performance design can be achieved in nonlinear control systems. Linear matrix inequality (LMI) techniques are employed to solve this robust fuzzy control problem. PI control structure is used and the control gains are determined based on $H^{\infty}$ control.

• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.117-124
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• 2016

Solar photovoltaic pumping system is one of most important of renewable energy applications especially in rural areas. Besides, the control strategy for standalone solar pumping system based on induction motor and without DC/DC converter has been widely studied and discussed in the literature. This topology is of great concern due its economic issues, especially when a standard frequency converter (SFCs) with scalar control is used instead of a dedicated PV inverter. This paper proposes an external control module to generate SFCs frequency reference in order to ensure both maximum power point tracking (MPPT). We present method of modeling and control of photovoltaic pumping system based centrifugal pump controlled by new improved incremental conductance in order to optimize the price and operation of pumping system this MPPT algorithm have many advantages like can be eliminate proportional integral controller It is a low cost solution since it requires no additional power equipment. The induction motor driven pump that is powered by a solar array is controlled by the indirect field oriented control (IFOC). The effectiveness of the proposed approach is illustrated by simulations carried out under Matlab Software. The experimental results are compared with simulation results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
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• pp.139-141
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• 2000

High voltage direct current(HVDC) transmission system uses the phase controlled rectifier triggered by means of IPC(individual phase control) or EPC(equidistant pulse control). Most HVDC system has adopted EPC method that can solve the harmonic instability problem of IPC method in weak power system. But EPC has inherent indirect synchronizing problem requiring the closed loop control. This paper presents the new gate pulse generating method for 12-pulse HVDC converter, which combines IPC with EPC. Simulation and test results are presented. The basic concept is that it generates the gating pulse for 12-pulse converter by synthesizing the internal phase reference using the frequency and phase information of a sin91e phase voltage. To ensure the reliability of the external phase input, Potential transformer that detects the phase voltage has redundancy. Using fault detecting algorithm the healthy input is always guaranteed. And the frequency compensation function was reinforced.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• 제어로봇시스템학회논문지
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• 제6권4호
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• pp.320-326
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• 2000

The real-time simulator of a pneumatic actuation system that is composed of differential PWM signal generator, charge solenoid valve, discharge solenoid valve, actuator, load, and rotational potentiometer is developed using a DSP board and a PC. The simulator receives the control signals from the external controller through the A/D converter, updates the state and output variables of the Pneumatic actuation system responding to the input signals every sampling time, and sends out the output signals through the D/A converter in real time. The user can observe the displacements, velocities, pressures, and mass flows representing the operation of pneumatic actuation system through the PC monitor in real time. Also the user can see the moving images between the pistons and rotating arm realistically in real time. The accuracy of the real-time simulator is verified by the good agreement of the real-time simulation results and the experimental results of the pneumatic actuation system.

• 한국CDE학회논문집
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• 제4권4호
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• pp.381-390
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• 1999

In this study, a pseudo ship structure data model for the :.hip cargo hold structure based on STEP is proposed. The proposed data model is based on Application Reference Model of AP218 Ship Structure which is the model that specifies conceptual structures and constraints used to describe the information requirements of an application. And the proposeddata model refers the Ship Common Model framework for the model architecture which is the basis for ongoing ship AP development within the ISO ship-building group and the ship product definition information model of CSDP research project for analyzing the relationship between ship structure model entities. The proposed data model includes Space, Compartment. Ship Structural System, Structural Part and Structural Feature of cargo hold. To generate this data model schema in EXPRESS format, ‘GX-Converter’was used which enables user to edit a model in EXPRESS format and convert schema file in EXPRESS format. Using this model schema, STEP physical file containing design data for ship cargo hold data structure was generated through SDAI programming. The another STEP physical file was also generated containing geometry data of ship cargo hold which was extracted and calculated by SDAI and external surface/surface intersection program. The geometry information of ship cargo hold can be then transferred to commercial CAD system, for example, Pro/Engineer. Examples of the modification of the design information are also Presented.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.376-382
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• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.