• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.1051-1054
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• 2000

We developed the micro CSF (celebrospinal fluid) shunt valve with surface and bulk micromachining technology in polymer MEMS. This micro CSF shunt valve was formed with four micro check valves to have a membrane connected to the anchor with the four bridges. The up-down movement of the membrane made the CSF on & off and the valve characteristic such as open pressure was controlled by the thickness and shape of the bridge and the membrane. The membrane, anchor and bridge layer were made of the $O_2$ RIE (reactive ion etching) patterned Parylene thin film to be about 5~10 microns in thickness on the silicon wafer. The dimension of the rectangular nozzle is 0.2＊0.2 $\textrm{mm}^2$ and the membrane 0.45 mm in diameter. The bridge width is designed variously from 0.04 mm to 0.12 mm to control the valve characteristics. To protect the membrane and bridge in the CSF flow, we developed the packaging system for the CSF micro shunt valve with the deep RIE of the silicon wafer. Using this package, we can control the gap size between the membrane and the nozzle, and protect the bridge not to be broken in the flow. The total dimension of the assembled system is 2.5＊2.5 $\textrm{mm}^2$ in square, 0.8 mm in height. We could precisely control the burst pressure and low rate of the valve varing the design parameters, and develop the whole CSF shunt system using this polymer MEMS fabricated CSF shunt valve.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.38-44
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• 2000

In this paper, we have been fabricated λ/2 phase plates lot an optical pick-up using a blue violet laser diode by employing proton exchange and wet etching in LiNbO$_{3}$. Their functions and fabrication processes are described in detail. It is established the optimal fabrication conditions through the experimental results. The device characteristics are measured by the Mach-zender interferometer which is composed of the optical components and 632.8nm He-Ne laser. The measured phase error was ＋5$^{\circ}$~ -6$^{\circ}$(within 3%). This phase plate could be applied an useful device to improve the resolution and the stability of the optical pick-up which has a blue violet laser diode as an optical source.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.2004-2006
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• 1996

A thermally driven polysilicon micro actuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS (tetracthylorthosilicate) as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE (vapor phase etching) process was also used as an effective release method for the elimination of sacrificial TEOS layer. The thickneas of polysilicon is $2{\mu}m$ and the lengths of active and passive polysilicon cantilevers are $500{\mu}m$ and $260{\mu}m$, respectively. The actuation is incurred by die thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon micro actuator was experimentally conformed as large as $21{\mu}m$ at the input voltage level of 10V and 50Hz square wave. The actuating characteristics are investigated by simulating the phenomena of heat transfer and thermal expansion in the polysilicon layer. The displacement of actuator is analyzed to be proportional to the square of input voltage. These micro actuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as micro relay, which requires large displacement or contact force but relatively slow response.

• Journal of Radiation Protection and Research
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• v.9 no.2
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• pp.55-60
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• 1984

The optimum etching condition of allyl diglycol carbonate (CR-39) for detecting the 60 MeV N-ions was determined as $70^{\circ}C$, 20% NaOH for 130min, by considering the variations of track density and diameter. Under these conditions, the maximum detectable track density was $1.7{\times}10^7tr/cm^2$. Track densities were linearly increased with increase of the total charge of the incident 60 MeV N-ions. By considering the scattring of N-ions as the Rutherford elastic scattering of point source, the measured relative probability was well consistent with the calculated value. The detection efficiency of CR-39 was in the range of 54-41% for 60 MeV N-ions of 12 nC-100 nC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.210-210
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• 2011

The effects of CH2F2 and N2 gas flow rates on the etch selectivity of silicon nitride (Si3N4) layers to extreme ultra-violet (EUV) resist and the variation of the line edge roughness (LER) of the EUV resist and Si3N4 pattern were investigated during etching of a Si3N4/EUV resist structure in dual-frequency superimposed CH2F2/N2/Ar capacitive coupled plasmas (DFS-CCP). The flow rates of CH2F2 and N2 gases played a critical role in determining the process window for ultra-high etch selectivity of Si3N4/EUV resist due to disproportionate changes in the degree of polymerization on the Si3N4 and EUV resist surfaces. Increasing the CH2F2 flow rate resulted in a smaller steady state CHxFy thickness on the Si3N4 and, in turn, enhanced the Si3N4 etch rate due to enhanced SiF4 formation, while a CHxFy layer was deposited on the EUV resist surface protecting the resist under certain N2 flow conditions. The LER values of the etched resist tended to increase at higher CH2F2 flow rates compared to the lower CH2F2 flow rates that resulted from the increased degree of polymerization.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Journal of Hydrogen and New Energy
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• v.13 no.3
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• pp.224-232
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• 2002

CdS-$TiO_2$ nano-composite sol was prepared by the sol-gel method in organic solvents at room temperature and further hydrothermal treatment at various temperatures to control the physical properties of the primary particles. Again, CdS-$TiO_2$ composite particulate films were made by casting CdS-$TiO_2$ sols onto $F:SnO_2$ conducting glass and then heat-treatment at $400^{\circ}C$. Physical properties of these 61ms were further controlled by the surface treatment with $TiCl_4$, aqueous solution. The photo currents and hydrogen production rates measured under the experimental conditions varied according to the $CdS/[CdS+TiO_2]$ mole ratio and the mixed-sol preparation method. For $CdS-TiO_2$ composite sols prepared in IPA, CdS particles were homogeneously surrounded by $TiO_2$ particles. Also, the surface treatment with $TiCl_4$ aqueous solution caused a considerable improvement in the photocatalytic activity, probably as a result of close contacts between the primary particles by the etching effect of $TiCl_4$. It was found that the photoelectrochemical performance of these particulate films could be effectively enhanced by this approach.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.83-86
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• 2002

In this paper, $3^{rd}$ overtone mode energy-trapped filter using modified $PbTiO_3$ system ceramics was manufactured to apply for intermediate frequency SMD-type filter with the variations of splitted electrode size. To investigate the effects of splitted electrode size on filter characteristics of $3^{rd}$ overtone mode energy-trapped filter, ceramic wafers were fabricated by etching splitted rectangular electrode size($b{\times}d$) of b=0.4, 0.6, 0.8, 1mm, d=0.3, 0.4, 0.5mm, respectively. And then, SMD-type ceramic filter were fabricated with the size of $3.7{\times}3.1mm$. With the variations of b size, insertion loss, 3dB bandwidth and 25dB stop bandwidth showed nearly constant value, but with the variations of d size, insertion loss, 3dB bandwidth, selectivity(shape factor) decreased.⨀؀က?⨀Ⴣ?⨀਀Ⴣ?⨀ꞻꎀ̀ကꮻꎀༀ뮻ꎀ᠀Ȁ햻ꎀĀힻꎀȀ?ꎀ̀?ꎀȀꎀĀꎀĀꎀĀꎀĀꎀЀȀꎀࠀꎀഀڼꎀഀᒼꎀ؀ᮼꎀ䈀ȀȀ悼ꎀऀ檼ꎀഀȀ禼ꎀഀ螼ꎀऀȀȀ鎼ꎀഀȀꊼꎀഀ낼ꎀࠀ즼ꎀԀ쾼ꎀ܀ힼꎀ

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.51-55
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• 2011

In this paper, the optimized doping condition of crystalline silicon solar cells with 156 ${\times}$ 156 mm2 area was studied. To optimize the drive-in condition in the doping process, the other conditions except drive-in temperature and time were fixed. After etching 7 ${\mu}m$ of the surface to form the pyramidal structure, the silicon nitride deposited by the PECVD had 75~80 nm thickness and 2 to 2.1 for a refractive index. The silver and aluminium electrodes for front and back sheet, respectively, were formed by screen-printing method, followed by firing in $400-425-450-550-850^{\circ}C$ five-zone temperature conditions to make the ohmic contact. Drive-in temperature was changed in range of $828^{\circ}C$ to $860^{\circ}C$ and time was from 3 min to 40 min. The sheet resistance of wafer was fixed to avoid its effect on solar cell. The solar cell fabricated with various conditions showed the similar conversion efficiency of 17.4%. This experimental result showed the drive-in temperatures and times little influence on solar cell characteristics.