• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.448-448
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• 2010

Magnetic random access memory (MRAM) has made a prominent progress in memory performance and has brought a bright prospect for the next generation nonvolatile memory technologies due to its excellent advantages. Dry etching process of magnetic thin films is one of the important issues for the magnetic devices such as magnetic tunneling junctions (MTJs) based MRAM. CoFeB is a well-known soft ferromagnetic material, of particular interest for magnetic tunnel junctions (MTJs) and other devices based on tunneling magneto-resistance (TMR), such as spin-transfer-torque MRAM. One particular example is the CoFeB - MgO - CoFeB system, which has already been integrated in MRAM. In all of these applications, knowledge of control over the etching properties of CoFeB is crucial. Recently, transferring the pattern by using milling is a commonly used, although the redeposition of back-sputtered etch products on the sidewalls and the low etch rate of this method are main disadvantages. So the other method which has reported about much higher etch rates of >$50{\AA}/s$ for magnetic multi-layer structures using $Cl_2$/Ar plasmas is proposed. However, the chlorinated etch residues on the sidewalls of the etched features tend to severely corrode the magnetic material. Besides avoiding corrosion, during etching facets format the sidewalls of the mask due to physical sputtering of the mask material. Therefore, in this work, magnetic material such as CoFeB was etched in an ICP etching system using the gases which can be expected to form volatile metallo-organic compounds. As the gases, carbon monoxide (CO) and ammonia ($NH_3$) were used as etching gases to form carbonyl volatiles, and the etched features of CoFeB thin films under by Ta masking material were observed with electron microscopy to confirm etched resolution. And the etch conditions such as bias power, gas combination flow, process pressure, and source power were varied to find out and control the properties of magnetic layer during the process.

• Korean Journal of Optics and Photonics
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• v.8 no.4
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• pp.345-352
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• 1997

Recently, in designing optical mask such as 4GDRAM, the scattering effect of electromagnetic wave must be considered. For this reason we claculated directly the mask function using the finite difference time domain(FDTD) method. The modification of image theory with this new mask function could explain clearly the scattering effect at the etched side wall of the submicron optical mask. The characteristics of the various type of alternating PSM were investigated. According to the simulation, the dual wet etch process was the most useful fabrication technique to overcoe the light scattering off at the shifted opening.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1977-1979
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• 1996

Single-crystaIline silicon diaphgrams and features are fabricated without using an etch stop process. The process involves vertical dry etching, double-sided alignment, followed by wet-chemical etching from the back side. The abvantages of this process are that $5{\sim}50{\mu}m$ diaphgrams and features can be fabricated accurately and inexpensively. In addition, since no impurity-based process is introduced, highly uniform and homogenous properties can be achieved

• Corrosion Science and Technology
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• v.2 no.5
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• pp.243-246
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• 2003

We have used a plasma etching method in order to develop a concave-type Pt electrode capacitor to overcome the limitation of conventional stack-type capacitor in a small critical-dimension (CD) pattern. We have deposited Pt layer on the concave-type structure made by patterning of $SiO_2$ and subsequently we separated the adjacent nodes by etch-back process with photoresist (PR) as a protecting layer.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Current Photovoltaic Research
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• v.4 no.2
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• pp.54-58
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• 2016

Laser-doped selective emitter process requires dopant source deposition, spin-on-glass, and is able to form selective emitter through SiNx layer by laser irradiation on desired locations. However, after laser doping process, the remaining dopant layer needs to be washed out. Laser-induced melting of pre-deposited impurity doping is a precise selective doping method minimizing addition of process steps. In this study, we introduce a novel scheme for fabricating highly efficient selective emitter solar cell by laser doping. During this process, laser induced damage induces front contact destabilization due to the hindrance of silver nucleation even though laser doping has a potential of commercialization with simple process concept. When the laser induced damage is effectively removed using solution etch back process, the disadvantage of laser doping was effectively removed. The devices fabricated using laser doping scheme power conversion efficiency was significantly improved about 1% abs. after removal the laser damages.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Journal of Sensor Science and Technology
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• v.24 no.4
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• pp.274-279
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• 2015

This paper describes optimizing fabrication methods for 2-axis electrically levitated MEMS gyroscope. Electrostatically levitated gyroscope has very high potential of performance due to the fact that its proof mass is not mechanically bound to any other structures, but its complex structure and difficulty of fabrication holds back the research that only a few researches have been reported. In this work, fabrication method for glass-silicon-glass 3-floor structure for 2-axis electrically levitated MEMS gyroscope is presented, including simplified multi-level glass etch method utilizing photoresist attack, preventing metal diffusion by adding middle layer of metal electrode, overcoming Deep RIE limitation by separate fabrication of silicon structures and keeping the electrode safe from dicing debris.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.198-205
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• 1992

Abstract-Planarieation technology, which is essential to VLSI, has been developed using non-etch back Spin- On-Glass (SOG). Process factors for 1.5 micron double metal technology are optimized by the statistical design of experiments. Optimum conditions are found to be a process with twice SOG coating, sufficiently long hot plate baking at 300t, and furnace curing for 40 minutes below 400$^{\circ}$C.