• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1579-1588
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• 2014

The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.26-38
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• 2015

고집적화를 위한 Floating Gate NAND 개발과정에서 몇 차례 기술적 한계상황에 직면하였었지만, Air-Gap, Double patterning, Multi-level Cell, Error Correction Code과 같은 breakthrough idea 을 활용하여 1Xnm까지 성공적인 scale-down 을 하였고 10nm 까지도 바라보고 있지만, 10nm 미만으로는 적절한 방안을 찾지 못한 상황입니다. CTD 의 3D NAND Flash는 Aspect Ratio, Poly channel의 intrinsic 특성, Data 보존 능력 등 해결 해야 할 issue 들이 남아 있지만, F.G Flash 의 지난 20년간 Lesson-learn 과 Band engineering, Channel Si, PUC 의 요소기술 개발 및 System algorithm 개발, QLC 개발 등을 통하여 F.G Flash를 넘어 지속적인 Cost-down 이 가능할 것입니다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.4
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• pp.286-292
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• 2011

Biometrics systems are used in a wide range of areas, including the area of crime prevention, due to their unique characteristics. However, serious problems can occur if biometric information is disclosed to an unauthorized user. To address these issues, this paper proposes a real valued fuzzy vault method, which adopts a real number error correction code to implement a fuzzy vault scheme for protecting fingerprint temples. The proposed method provides the benefit of allowing the private key value to be changed at any time, unlike biometric template such as a fingerprint, which is not easily renewable even if its security has been breached. The validity of the proposed method is verified for fingerprint verification.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.77-80
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• 2005

Wireless sensor networks(WSN) technology has various applications such as surveillance and information gathering in the uncontrollable area of human. One of major issues in WSN is the research for reducing the energy consumption and reliability of data. A system with forward error correction(FEC) can provide an objective reliability while using less transmission power than a system without FEC. In this paper, we propose to use LDPC codes of various code rate(0.53, 0.81, 0.91) for FEC for WSN. Also, we considered node-to-node interference in addition to AWGN channel. The proposed system has not only high reliable data transmission at low SNR, but also reduced transmission power usage.

• The Journal of Information Technology
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• v.3 no.1
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• pp.29-36
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• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.109-112
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• 2003

본 논문에서는 확장 유클리드 알고리즘을 이용하여 VLSI 구현에 적합한 GF(2/sup m/)에서의 나눗셈 알고리즘을 제안하였다. 제안하는 나눗셈 알고리즘은 GF(2/sup m/)에서 2m-2번의 반복적인 비트 연산을 필요로 하며 입력 데이터에 의존적인 하드웨어 구조를 새로운 (m+1)-bit의 유한체 G와 H를 도입하여 간단하게 제어하도록 구현하였다. 본 논문에서 제안하는 알고리즘은 유한체 곱셈과 나눗셈이 요구되는 Error Correction Code와 암호 알고리즘에 효율적으로 적용이 가능하다. 현재 대표적으로 사용되는 기존 나눗셈 알고리즘과 비교해 볼 때 연산 시간은 비슷하지만 2-bit의 제어신호만을 필요로 하기 때문에 입력 데이터에 독립적인 O(1)의 complexity를 가짐으로 O(log₂(m+1))의 컨트롤을 갖는 다른 두 알고리즘에 비해 하드웨어 리소스 면에서 월등한 결과를 보인다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1026-1030
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• 2015

In this paper, we propose a signal processing board of an optical delay simulator for evaluating a long-range laser range finder and a laser target designator. We improved the accuracy by applying the clock multiplication and the correction of error gradient. To evaluate the performance of the proposed method, we implemented a prototype board and performed experiments. As a result, we implemented the optical delay simulator with resolution less than 0.7m in measuring distance 60km and a standard deviation of 0.041m. The PRF code detection logic and generation logic have a stability less than 0.03% and 0.08% compared to the NATO standard, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.