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Study of a Low-power Error Correction Circuit for Image Processing  

Lee, Sang-Jun (연세대학교 전기전자공학과 프로세서 연구실)
Park, Jong-Su (연세대학교 전기전자공학과 프로세서 연구실)
Jeon, Ho-Yun (연세대학교 전기전자공학과 프로세서 연구실)
Lee, Yong-Surk (연세대학교 전기전자공학과 프로세서 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.33, no.10C, 2008 , pp. 798-804 More about this Journal
Abstract
This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.
Keywords
L2 Cache ECC; Low Power ECC;
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