• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.36-42
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• 2007

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.133-139
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• 2002

In precision instrumentation system, an A/D conversion of signal conditioning has been always suffered from some problems ; offset and drift voltage with environmental situation. This paper suggests a method of reducing the offset voltage and the drift error from the A/D conversion hardware using analog signal switching technique with specific operational amplifier circuits. Also, we have designed a hardware active filter and a software digital filter with Auto Zero Tracking algorithm for better dignal process of the our proposed weighing system. Software technique was performed to obtain the stable data from A/D converter. As a result of our experimental works, the proposed system is expected to be used in the industrial field where a high precision measurement is required.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.4
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• pp.224-230
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• 2006

The conventional way to implement a bidirectional converter with boost/buck has been to use two general purpose PWM ICs with a single supply voltage. In this case, when one direction mode is in operation, the other is disabled and the output of the error amplifier of the disabled IC may be saturated to a maximum value or zero. Therefore, during mode transition, a circuit which can disable the switching operation for a certain time interval is required making it impossible to get a seamless transition. In this paper, the limitations of the conventional 42V/14V bi-directional DC/DC converter implemented with general current mode PWM ICs with a single supply voltage are reviewed and a new current mode PWM controller circuit with a dual voltage system is proposed. The validity of the proposed circuit is investigated through simulation. and experiments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.161-161
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• 2010

In order to achieve low power consumption and the uniform power spectrum of LED BLU (Back Light Unit) system, new circuits with a 2 stage L-C (Inductor-Capacitor) coupler have been proposed. From the simulation results based on our proposed model, the ripple power of the L-C regulation-embedded BLU circuit shows a dramatic reduction by more than 89.3% as compared to the normal BLU (without L-C circuits). This indicates that the proposed circuit is very promising for the realization of high-efficiency BLU circuits.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.369-372
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• 2002

This paper presents a family of continuous conduction mode with constant-switching pulse width modulator controllers. Unified implementation of quasi steady state approach for various DC-DC converters topoiogies is illustrated. The property and control low for quasi-state approach will be discussed in this paper. The different procedures will be discussed in details with different results for five commonly used DC-DC converters. Both trailing and leading edge pulse width modulation are used. Leading edge modulation can some times lead to simpler control circuitry as will be demonstrated in some circuits. These controllers do not require the multiplier in the voltage feed back loop, error amplifier in the current loop and rectified line voltage sensor, which are needed by traditional control methods. Controller examples and design arc analyzed.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1030-1033
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• 2002

This paper, a new simple controller operates in continuous conduction mode (CCM) for Boost power factor collection converter is introduced. The duty ratios are obtained by comparisons of a sensed signal from inductor current and a negative ramp carrier waveform in each switching period. By using the proposed controller, input voltage sensing, error amplifier in the current feedback loop, and analog multiplier／divider are not required, then, the control circuit implementation is very simple. To verify the proposed controller, the circuit simulation for Boost power factor correction converter was applied. For the results, the input current waveform was shaped to be closely sinusoidal, implying low THD.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.975-978
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• 2003

본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.3
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• pp.7-12
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• 2005

In this paper, we used class D amplification circuit to improve the decline of error rate caused by low impedance in the Power Line Communication. We manufactured voltage drive circuit and current drive circuit that are driven circuit of power line modem on the present and made a comparison experiment with drivel circuit that uses class D amplifier proposed in this paper. As a result of Experiment, We showed that it has great superiority over other existing drive circuits at rapid impedance change in power line channel.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.6
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• pp.24-29
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• 1976

A study is presented on the DDM (double delta modulation) system which incorporates another modulation loop in front of the delta modulation system. DDM is proposed to delta modulate the error signal which is derivated through the ordinary delta modulation. This system is constructed simply by adding a differential amplifier and an integrator to the basic DM system. Since signal-to-quantization noise ratio SNR is the most informative measure of quantizer performance, the formula of the max. SNR of the DDM system is derived and investigated experimentally for a sinusoidal input. The max. SNR of the DDM is larger than that of DM in low bit rate region and vice versa in high bit rate region.