• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.701-704
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• 2011

The reliability of a computer system largely depends on that of its memory systems, which are vulnerable to soft errors. Soft errors can be coped with a combination of an Error Detection & Correction circuit and scrubbing operation. Smaller geometries and lower voltage of advanced memories makes them more prone to suffer multibit soft errors. A memory structure against multibit soft errors and a suitable scrubbing scheme for it were proposed. This paper introduces a key issue for the scrubbing of the memories with protection against multibit soft errors and the result of the performance analysis from a reliability point of view.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.44-52
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• 2017

In this paper, we propose a DFD (Digital Frequency Discriminator) design that has better frequency discrimination and a smaller size. Electronic warfare equipment can analyze different types of radar signal such as those based on Frequency, Pulse Width, Time Of Arrival, Pulse Amplitude, Angle Of Arrival and Modulation On Pulse. In order for electronic warfare equipment to analyze radar signals with a narrow pulse width (less than 100ns), they need to have a special receiver structure called IFM (Instantaneous Frequency Measurement). The DFD (Digital Frequency Discriminator) is usually used for the IFM. Because the existing DFDs are composed of separate circuit devices, they are bulky, heavy, and expensive. To remedy these shortcomings, we use a three delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$) in the DFD, instead of the four delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$, $64{\lambda}$) generally used in the existing DFDs, and apply the microwave integrated circuit method. To enhance the frequency discrimination, we detect the pulse amplitude and perform temperature correction. The proposed DFD has a frequency discrimination error of less than 1.5MHz, affording it better performance than imported DFDs.

• Korean Chemical Engineering Research
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• v.60 no.3
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• pp.363-370
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• 2022

In this paper, an estimation algorithm for state of charge (SOC) was applied using an equivalent circuit model (ECM) and an Extended Kalman Filter (EKF) to improve the estimation accuracy of the battery system states. In particular, an observer was designed to estimate SOC along with the aged capacity. In the case of the fresh battery, when SOC was estimated by Kalman Filter (KF), the mean absolute percentage error (MAPE) was 0.27% which was smaller than MAPE of 1.43% when the SOC was calculated by the model without the observer. In the driving mode of the vehicle, the general KF or EKF algorithm cannot be used to estimate both SOC and capacity. Considering that the battery aging does not occur in a short period of time, a strategy of periodically estimating the battery capacity during charging was proposed. In the charging mode, since the current is fixed at some intervals, a strategy for estimating the capacity along with the SOC in this situation was suggested. When the current was fixed, MAPE of SOC estimation was 0.54%, and the MAPE of capacity estimation was 2.24%. Since the current is fixed when charging, it is feasible to estimate the battery capacity and SOC simultaneously using the general EKF. This method can be used to periodically perform battery capacity correction when charging the battery. When driving, the SOC can be estimated using EKF with the corrected capacity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.36-46
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• 2017

The turbo code, an error correction code, needs a long decoding time since the same decoding process must be repeated several times in order to obtain a good BER performance. Thus, parallel processing may be used to reduce the decoding time, in which case there may be a memory contention that requires additional buffers. The QPP interleaving has been proposed to avoid such case, but there is still a possibility of memory contention when a decoder is constructed using the so-called double flow technique. In this paper, we propose an even-odd cross mapping technique to avoid memory conflicts even in decoding using the double-flow technique. This method uses the address generation characteristic of the QPP interleaving and can be used to implement the interleaving circuit between the decoding blocks and the LLR memory blocks. When the decoder implemented by applying the double flow and the proposed methods is compared with the decoder by the conventional MDF techniques, the decoding time is reduced by up to 32% with the total area increase by 8%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.673-676
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• 2008

In wireless communications such as Bluetooth, Baseband should be able to minimize the DC bias of the data which passed the modem interface of either transmitter or receiver for the reliability of the circuit and the integrity of the data. The transmitter scrambles the data to send randomly to the error correction block and the receiver recovers the randomly spread data as they have been. To design the whitening block, it is important to select the prime polynomial for the filtering. In this paper, we designed a optimal whitening block using the prime polynomial $g(D)=D^7+D^4+1$ for hardware and area efficiency. The proposed hardware whitening block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized whitening block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.30-37
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• 2007

An exponentiation in $GF(2^m)$ is a basic operation for several algorithms used in cryptography, digital signal processing, error-correction code and so on. Existing hardware implementations for the exponentiation operation organize by Right-to-Left method since a merit of parallel circuit. Our paper proposes a polynomial exponentiation structure with a trinomial that is organized by Left-to-Right method and that utilizes a weakly dual basis. The basic idea of our method is to decrease time delay using precomputation tables because one of two inputs in the Left-to-Right method is fixed. Since $T_{sqr}$ (squarer time delay) + $T_{mul}$(multiplier time delay) of ow method is smaller than $T_{mul}$ of existing methods, our method reduces time delays of existing Left-to-Right and Right-to-Left methods by each 17%, 10% for $x^m+x+1$ (irreducible polynomial), by each 21%, 9% $x^m+x^k+1(1, by each 15%, 1% for $x^m+x^{m/2}+1$.