• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.204-210
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• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.13-22
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• 1991

In this paper we designed 2 bit ECC(Error Checking and Correction) circuit using Single Layer Perceptron type neural networks. We used (11, 6) block codes having 6 data bits and 8 check bits with appling cyclic hamming codes. All of the circuits are layouted by CMOs 2um double metal design rules. In the result of circuit simulation, 2 bit ECC circuit operates at 67MHz of input frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.309-316
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• 1986

A concatenated coding system using a binary code as the inner code and a nonbinary code as the outer code has been constructed for the purpose of error correction. The complexity of a conventional coding system grows exponentially as the code length of a block code becomes longer. To reduce the complexity for ling code, an effective communication system has been proposed by cascading two codes-binary and norbinary codes. Using a parallel-to-serial circuit and a serial-to-parallel circuit, the concatenated coding system has been designed and constructed by empolying a (7,3) burst error correcting code as the inner code and a (7,3) Reed-Solomon code as the outer code. This system has been simulated and tested using a micro-computer. For the (49,9) concatenated coding system, the error probability of the channel has been evaluated and compared to different coding systems.

• The Journal of the Korea Contents Association
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• v.8 no.10
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• pp.37-44
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• 2008

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.45-52
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• 2004

This Paper presents a modified hard decision Viterbi decoder with an error prediction circuit enhancing performance for the burst error inputs. Viterbi decoder employs the maximum likelihood decoding algorithm which shows excellent error correction capability for the random error inputs. Viterbi decoders, however, suffer poor error correction performance for the burst error inputs under the fading channel. The proposed error prediction algorithm increases error correction capability for the burst errors. The algorithm estimaties the burst error data area using the maximum path metric for the erroneous inputs, It calculates burst error intervals based on increases in the maximum values of a path metric. The proposed decoder keeps a performance the same as the conventional decoders on AWGN channels for the IEEE802.l1a WLAN system. It shows performance inproving 15% on the burst error of multi-path fading channels, widely used in mobile systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.83-92
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• 2004

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.

• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.229-233
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• 2009

This paper proposes a correction method for the error inherently created by time-step approximation in finite element analysis (FEA). For a simple RL and RLC linear circuit, the error in time-step analysis is analytically investigated, and a correction method is proposed for a non-linear system as well as a linear one. Then, for a practical inductor model, linear and non-linear time-step analyses are performed and the calculation results are corrected by the proposed methods. The accuracy of the corrected results is confirmed by comparing the electric input and output powers.