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Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit  

Kim, Won (LG전자 MC사업부)
Seon, Jong-Kug (LS 산전)
Yoon, Kwang-Sub (인하대학교 전자공학과 정보전자 공동 연구소)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.35, no.5A, 2010 , pp. 504-512 More about this Journal
Abstract
The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.
Keywords
ADC(Analog-to-Digital Converter); Flash; Error Correction Circuit;
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