• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1992.11a
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• pp.127-130
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• 1992

GF(2m) 이론은 switching 이론과 컴퓨터 연산, 오류 정정 부호(error correcting codes), 암호학(cryptography) 등에 대한 폭넓은 응용 때문에 주목을 받아 왔다. 특히 유한체에서의 이산 대수(discrete logarithm)는 one-way 함수의 대표적인 예로서 Massey-Omura Scheme을 비롯한 여러 암호에서 사용하고 있다. 이러한 암호 system에서는 암호화 시간을 동일하게 두면 고속 연산은 유한체의 크기를 크게 할 수 있어 비도(crypto-degree)를 향상시킨다. 따라서 고속 연산의 필요성이 요구된다. 1981년 Massey와 Omura가 정규기저(normal basis)를 이용한 고속 연산 방법을 제시한 이래 Wang, Troung 둥 여러 사람이 이 방법의 구현(implementation) 및 곱셈기(Multiplier)의 설계에 힘써왔다. 1988년 Itoh와 Tsujii는 국제 정보 학회에서 유한체의 역원을 구하는 획기적인 방법을 제시했다. 1987년에 H, W. Lenstra와 Schoof는 유한체의 임의의 확대체는 원시정규기저(primitive normal basis)를 갖는다는 것을 증명하였다. 1991년 Stepanov와 Shparlinskiy는 유한체에서의 원시원소(primitive element), 정규기저를 찾는 고속 연산 알고리즘을 개발하였다. 이 논문에서는 원시 정규기저를 찾는 Algorithm을 구현(Implementation)하고 이것이 응용되는 문제들에 관해서 연구했다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.156-163
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• 2013

The use of an error-correcting code is essential in communication systems where the channel is noisy. When channel coding parameters are unknown at a receiver side, decoding becomes difficult. To perform decoding without the channel coding information, we should estimate the parameters. In this paper, we introduce a method to reconstruct the generator polynomial of BCH(Bose-Chaudhuri-Hocquenghem) codes based on the idea that the generator polynomial is compose of minimal polynomials and BCH code is cyclic code. We present a probability compensation method to improve the reconstruction performance. This is based on the concept that a random data pattern can also be divisible by a minimal polynomial of the generator polynomial. And we confirm the performance improvement through an intensive computer simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.39-48
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• 2004

Turbo codes, whose performance in bit error rate is close to the Shannon limit, have been adopted as a part of standard for the third-generation high-speed wireless data services. Iterative Turbo decoding results in decoding delay and high power consumption. As wireless communication systems can only use limited power supply, low power design techniques are essential for mobile device implementation. This paper proposes new effective criteria for stopping the iteration process in turbo decoding to reduce power consumption. By setting two stopping criteria, decodable threshold and undecodable threshold, we can effectively reduce the number of decoding iterations with only negligible error-correcting performance degradation. Simulation results show that the number of unsuccessful error-correction can be reduced by 89% and the number of decoding iterations can be reduced by 29% on the average among 12500 simulations when compared with those of an existing typical method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.97-103
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• 2004

In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.

• Journal of Advanced Navigation Technology
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• v.15 no.5
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• pp.781-788
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• 2011

A sphere-packing problem is to find an arrangement of the spheres to fill as large area of the given space as possible, and covering problems are optimization problems which are dual problems to the packing problems. We generalize the concepts of the weight and the Hamming distance for a binary code to those of Boolean algebra. In this paper, we define a weight and a distance on a Boolean algebra and research some properties of the weight and the distance. Also, we prove the notions of the sphere-packing bound and the Gilbert-Varshamov bound on Boolean algebra.