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http://dx.doi.org/10.14372/IEMEK.2016.11.4.227

Low Latency Systolic Multiplier over GF(2m) Using Irreducible AOP  

Kim, Kee-Won (Dankook University)
Han, Seung-Chul (Myongji University)
Publication Information
IEMEK Journal of Embedded Systems and Applications / v.11, no.4, 2016 , pp. 227-233 More about this Journal
Abstract
Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.
Keywords
Finite fields; All-one polynomial; Multiplication; VLSI;
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Times Cited By KSCI : 3  (Citation Analysis)
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