DOI QR코드

DOI QR Code

Simplified 2-Dimensional Scaled Min-Sum Algorithm for LDPC Decoder

  • Received : 2016.07.28
  • Accepted : 2016.12.26
  • Published : 2017.05.01

Abstract

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

Keywords

References

  1. Robert G. Gallager, "Low-Density Parity-Check Codes," IRE Trans. Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962. https://doi.org/10.1109/TIT.1962.1057683
  2. D. J. C. MacKay and R. M. Neal, "Near Shannon Limit Performance of Low Density Parity Check Codes," IET Electron. Lett., vol. 32, no. 18, pp. 1645, Aug. 1996. https://doi.org/10.1049/el:19961141
  3. L. Li, D. Qu, and T. Jiang, "Partition Optimization in LDPC-Coded OFDM Systems with PTS PAPR Reduction," IEEE Trans. Veh. Technol., vol. 63, no. 8, pp. 4108-4113, Oct. 2014. https://doi.org/10.1109/TVT.2014.2305153
  4. A. J. Wong, S. Hemati, and W. J. Gross, "Efficient Implementation of Structured Long Block-Length LDPC Codes," in 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Toronto, Canada, July 2015.
  5. Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, "Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM," IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 783-794, Mar. 2014. https://doi.org/10.1109/JSSC.2014.2300417
  6. Sae-Young Chung, G. D. Forney, T. J. Richardson, and R. Urbanke, "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit," IEEE Commun. Lett., vol. 5, no. 2, pp. 58-60, Feb. 2001. https://doi.org/10.1109/4234.905935
  7. Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: enhancements for higher throughput, IEEE Std. P802.11n/D7.0, 2008.
  8. IEEE 802.11ac-Enhancements for Very High Throughput for operation in bands below 6 GHz, IEEE P802.11ac/D5.0, 2013.
  9. IEEE P802.11ad: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications - Enhancements for Higher Throughput in the 60 GHz Band, IEEE, 2012.
  10. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE Std. 802.3an, 2006.
  11. R. Tanner, "A Recursive Approach to Low Complexity Codes," IEEE Trans. Inform. Theory, vol. 27, no. 5, pp. 533-547, Sep. 1981. https://doi.org/10.1109/TIT.1981.1056404
  12. J. Hagenauer, E. Offer, and L. Papke, "Iterative Decoding of Binary Block and Convolutional Codes," IEEE Trans. Inf. Theory, vol. 42, no. 2, pp. 429-445, Mar. 1996. https://doi.org/10.1109/18.485714
  13. J. Chen and M. Fossorier, "Near Optimum Universal Belief Propagation Based Decoding of Low Density Parity Check Codes," IEEE Trans. Commun., vol. COM-50, no. 3, pp. 406-414, Mar. 2002.
  14. J. Heo, "Analysis of Scaling Soft Information on Low Density Parity Check Code," IET Electron. Lett., vol. 39, no. 2, pp. 219, Jan. 2003. https://doi.org/10.1049/el:20030169
  15. S. L. Howard, C. Schlegel, and V. C. Gaudet, "Degree-Matched Check Node Decoding for Regular and Irregular LDPCs," IEEE Trans. Circuits Syst. II Express Briefs, vol. 53, no. 10, pp. 1054-1058, Oct. 2006. https://doi.org/10.1109/TCSII.2006.882204
  16. Y. Xu, L. Szczecinski, B. Rong, F. Labeau, D. He, Y. Wu, and W. Zhang, "Variable LLR Scaling in Min-Sum Decoding for Irregular LDPC Codes," IEEE Trans. Broadcast., vol. 60, no. 4, pp. 606-613, Dec. 2014. https://doi.org/10.1109/TBC.2014.2364532
  17. Ahmed A. Emran and Maha Elsabrouty "Generalized Simplified Variable-Scaled Min Sum LDPC Decoder for Irregular LDPC Codes," Personal, Indoor, and Mobile Radio Communication (PIMRC), 2014 IEEE 25th Annual International Symposium on, Washington DC, USA, Sep. 2014.
  18. Zhou Zhong, Shuming Guo, Xiangyang Xu, and Huiqing Bai, "A Classified Normalized BP-Based Algorithm with 2-Dimensional Correction for LDPC Codes," Journal of Communications, vol. 8, no. 5, May 2013
  19. R. Zarubica, R. Hinton, S. G. Wilson, and E. K. Hall, "Efficient Quantization Schemes for LDPC Decoders," in IEEE Military Communications Conference, San Diego, Nov. 2008.
  20. J. Zhao, F. Zarkeshvari, and A. H. Banihashemi, "On Implementation of Min-Sum Algorithm and Its Modifications for Decoding Low-Density Parity-Check (LDPC) Codes," IEEE Trans. Commun., vol. 53, no. 4, pp. 549-554, Apr. 2005. https://doi.org/10.1109/TCOMM.2004.836563
  21. V. A. Chandrasetty and S. M. Aziz, "FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm," in 2010 Second International Conference on Computer Research and Development, Kuala Lumpur, May 2010.
  22. C. L. Wey, M. D. Shieh and S. Y. Lin, "Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation," IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3430-3437, Dec. 2008. https://doi.org/10.1109/TCSI.2008.924892
  23. B. Xiang, R. Shen, A. Pan, D. Bao and X. Zeng, "An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes," IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 10, pp. 1447-1460, Sep. 2010. https://doi.org/10.1109/TVLSI.2009.2025169
  24. J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and Xiao-Yu Hu, "Reduced-Complexity Decoding of LDPC Codes," IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, Aug. 2005. https://doi.org/10.1109/TCOMM.2005.852852