• Title/Summary/Keyword: Error Check Algorithm

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Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors (오류 마루 현상이 완화된 비이진 LDPC 부호의 설계 및 성능 분석 연구)

  • Ahn, Seok-Ki;Lim, Seung-Chan;Yang, Youngoh;Yang, Kyeongcheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.10
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    • pp.852-857
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    • 2013
  • In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

Rate-Compatible LDPC Codes Based on the PEG Algorithm for Relay Communication Systems

  • Zhou, Yangzhao;Jiang, Xueqin;Lee, Moon Ho
    • Journal of Communications and Networks
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    • v.17 no.4
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    • pp.346-350
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    • 2015
  • It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

New Message-Passing Decoding Algorithm of LDPC Codes by Partitioning Check Nodes (체크 노드 분할에 의한 LDPC 부호의 새로운 메시지 전달 복호 알고리즘)

  • Kim Sung-Hwan;Jang Min-Ho;No Jong-Seon;Hong Song-Nam;Shin Dong-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4C
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    • pp.310-317
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    • 2006
  • In this paper, we propose a new sequential message-passing decoding algorithm of low-density parity-check (LDPC) codes by partitioning check nodes. This new decoding algorithm shows better bit error rate(BER) performance than that of the conventional message-passing decoding algorithm, especially for small number of iterations. Analytical results tell us that as the number of partitioned subsets of check nodes increases, the BER performance becomes better. We also derive the recursive equations for mean values of messages at variable nodes by using density evolution with Gaussian approximation. Simulation results also confirm the analytical results.

Fault Tolerant Cache for Soft Error (소프트에러 결함 허용 캐쉬)

  • Lee, Jong-Ho;Cho, Jun-Dong;Pyo, Jung-Yul;Park, Gi-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.1
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    • pp.128-136
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    • 2008
  • In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

On Combining Chase-2 and Sum-Product Algorithms for LDPC Codes

  • Tong, Sheng;Zheng, Huijuan
    • ETRI Journal
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    • v.34 no.4
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    • pp.629-632
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    • 2012
  • This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

New Min-sum LDPC Decoding Algorithm Using SNR-Considered Adaptive Scaling Factors

  • Jung, Yongmin;Jung, Yunho;Lee, Seongjoo;Kim, Jaeseok
    • ETRI Journal
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    • v.36 no.4
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    • pp.591-598
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    • 2014
  • This paper proposes a new min-sum algorithm for low-density parity-check decoding. In this paper, we first define the negative and positive effects of the received signal-to-noise ratio (SNR) in the min-sum decoding algorithm. To improve the performance of error correction by considering the negative and positive effects of the received SNR, the proposed algorithm applies adaptive scaling factors not only to extrinsic information but also to a received log-likelihood ratio. We also propose a combined variable and check node architecture to realize the proposed algorithm with low complexity. The simulation results show that the proposed algorithm achieves up to 0.4 dB coding gain with low complexity compared to existing min-sum-based algorithms.

An analysis of BER performance of LDPC decoder for WiMAX (WiMAX용 LDPC 복호기의 비트오율 성능 분석)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.771-774
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    • 2010
  • In this paper, BER performance of LDPC(Low-Density Parity-Check) decoder for WiMAX is analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by Matlab, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate(BER) performance of LDCP decoder. The parity check matrix for IEEE 802.16e standard which has block length of 2304 and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (8,6).

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A Weighted Block-by-Block Decoding Algorithm for CPM-QC-LDPC Code Using Neural Network

  • Xu, Zuohong;Zhu, Jiang;Zhang, Zixuan;Cheng, Qian
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.8
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    • pp.3749-3768
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    • 2018
  • As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

A Study on Error Detection Algorithm of COD Measurement Machine

  • Choi, Hyun-Seok;Song, Gyu-Moon;Kim, Tae-Yoon
    • Journal of the Korean Data and Information Science Society
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    • v.18 no.4
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    • pp.847-857
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    • 2007
  • This paper provides a statistical algorithm which detects COD (chemical oxygen demand) measurement machine error on real-time. For this we propose to use regression model fitting and check its validity against the current observations. The main idea is that the normal regression relation between COD measurement and other parameters inside the machine will be violated when the machine is out of order.

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DECODING OF LEXICODES S10,4

  • KIM, D.G.
    • Journal of the Korean Society for Industrial and Applied Mathematics
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    • v.6 no.1
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    • pp.47-52
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    • 2002
  • In this paper we propose a simple decoding algorithm for the 4-ary lexicographic codes (or lexicodes) of length 10 with minimum distance 4, write $S_{10,4}$. It is based on the syndrome decoding method. That is, using a syndrome vector we detect an error and it will be corrected an error from the four parity check equations.

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