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http://dx.doi.org/10.7840/kics.2013.38C.10.852

Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors  

Ahn, Seok-Ki (포항공과대학교 전자전기공학과 통신 및 신호설계 연구실)
Lim, Seung-Chan (포항공과대학)
Yang, Youngoh (제주대학교)
Yang, Kyeongcheol (포항공과대학교 전자전기공학과 통신 및 신호설계 연구실)
Abstract
In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.
Keywords
BPSK; cycle; error floor; importance sampling; nonbinary LDPC codes;
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