• Journal of Korea Society of Industrial Information Systems
• /
• v.17 no.7
• /
• pp.17-24
• /
• 2012

As the resources and power on Ad-hoc networks are limited, new data aggregation techniques are required for energy efficiency. The current research on data aggregation techniques is actively in progress, but existing studies don't consider the density of nodes. If nodes are densely placed in a particular area, the information which the sensor nodes placed on those areas detect can be judged as very strong association. But, the energy spent transmitting this information is a waste of energy. In this paper the densely-concentrated node area is designated as Hotspot_Zone in the multi-hop clustering environment using the AMC and a key node is selected in the area. If the request message of data aggregation is transmitted, the key node among the neighboring nodes sends its environmental information to a manager to avoid duplicate sensing information. Therefore, the life of networks can be prolonged due to this.

• Journal of Korea Society of Industrial Information Systems
• /
• v.11 no.2
• /
• pp.48-62
• /
• 2006

In recent years, wireless sensor networks(WSNs) have emerged as a new fast-growing application domain for wireless distributed computing and embedded systems. Recent Progress in computer and communication technology has made it possible to organize wireless sensor networks composed tiny sensor nodes. Furthermore, ad-hoc network protocols do not consider the characteristics of wireless sensor nodes, making existing ad-hoc network protocols unsuitable for the wireless sensor networks. First, we propose power-aware routing protocols based on energy-centered routing metrics. Second, we describe power management techniques for wireless sensor nodes using the spatial locality of sensed data. Many nodes can go into a power-down mode without sacrificing the accuracy of sensed data. Finally, combining the proposed techniques, we describe an overall energy-efficient protocol for data collection. Experimental results show that the proposed routing protocol can extend the routing path lifetime more than twice. The average energy consumption per sensing period is reduced by up to 30%.

• Journal of the Korean Solar Energy Society
• /
• v.22 no.3
• /
• pp.47-56
• /
• 2002

The office is an excellent candidate for implementing daylighting techniques because of the relatively high electric lighting power densities and long daytime use pattern. The quantity of light available for a space can be translated in term of the amount of energy savings through a process of a building energy simulation. To get significant energy savings in general illumination, the electric lighting system must be incorporated with a daylight - activated dimmer control. A prototype configuration of an office interior has been established and the integration between the building envelope and lighting and HVAC systems is evaluated based on computer modeling of a lighting control facility. First of all, an energy-efficient luminaire system is designed for both a totally open-plan office interior and a partitioned office. A lighting design and analysis program, Lumen-Micro 2000 predicts the optimal layout of a conventional fluorescent lighting fixture to meet the designed lighting level and calculates unit power density, which translates the demanded amount of electric lighting energy. A dimming control system integrated with the contribution of daylighting has been applied to the operating of the artificial lighting. Annual cooling load due to lighting and the projecting saving amount of cooling load due to daylighting under overcast diffuse sky are evaluated by a computer software, ENER-Win. In brief, the results from building energy simulation with measured daylight illumination levels and the performance of lighting control system indicate that daylighting can save over 70 percent of the required energy for general illumination in the perimeter zones through the year. A 25 % of electric energy for cooling may be saved by dimming and turning off the luminaires in the perimeter zones.

• ETRI Journal
• /
• v.43 no.4
• /
• pp.717-727
• /
• 2021

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current bestperforming techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

• Structural Engineering and Mechanics
• /
• v.81 no.5
• /
• pp.633-645
• /
• 2022

The active tuned mass damper (ATMD) is an efficient and reliable structural control system for mitigating the dynamic response of structures. The inertial force that an ATMD exerts on a structure to attenuate its otherwise large kinetic energy and undesirable vibrations and displacements is proportional to its excursion. Achieving a balance between the inertial force and excursion requires a control law or feedback mechanism. This study presents a technique for the optimum design of a sliding mode controller (SMC) as the control law for ATMD-equipped structures subjected to earthquakes. The technique includes optimizing an SMC under an artificial earthquake followed by testing its performance under real earthquakes. The SMC of a real 11-story shear building is optimized to demonstrate the technique, and its performance in mitigating the displacements of the building under benchmark near- and far-fault earthquakes is compared against that of a few other techniques (proportional-integral-derivative [PID], linear-quadratic regulator [LQR], and fuzzy logic control [FLC]). Results indicate that the optimum SMC outperforms PID and LQR and exhibits performance comparable to that of FLC in reducing displacements.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.11 no.2
• /
• pp.939-951
• /
• 2019

A novel empirical mode decomposition strategy based on Fourier transform and band-pass filter techniques, contributing to efficient instantaneous vibration analyses, is developed in this study. Two key improvements are proposed. The first is associated with the adoption of a band-pass filter technique for intrinsic mode function sifting. The primary characteristic of decomposed components is that their bandwidths do not overlap in the frequency domain. The second improvement concerns an attempt to design narrowband constraints as the essential requirements for intrinsic mode function to make it physically meaningful. Because all decomposed components are generated with respect to their intrinsic narrow bandwidth and strict sifting from high to low frequencies successively, they are orthogonal to each other and are thus suitable for an instantaneous frequency analysis. The direct Hilbert spectrum is employed to illustrate the instantaneous time-frequency-energy distribution. Commendable agreement between the illustrations of the proposed direct Hilbert spectrum and the traditional Fourier spectrum was observed. This method provides robust identifications of vibration modes embedded in vibration processes, deemed to be an efficient means to obtain valuable instantaneous information.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.2 s.344
• /
• pp.42-50
• /
• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
• /
• 2003.05a
• /
• pp.109-114
• /
• 2003

Wireless communication systems are inevitable for efficient underwater activities. Because of the poor propagation characteristics of light and electromagnetic waves, acoustic waves are generally used for the underwater wireless communication. Although there are many kinds of information type, visual images take an essential role especially for search and identification activities. For this reason, we developed an acoustic-based underwater image transmission system under a dual use technology project supported by MOCIE (Ministry of Commerce, Industry and Energy). For the application to complicated and time-varying underwater environments all-digital transmitter and receiver systems are investigated. Array acoustic transducers are used at the receiver, which have the center frequency of 32kHz and the bandwidth of 4kHz. To improve transmission speed and quality, various algorithms and systems are used. The system design techniques will be discussed in detail including image compression/ decompression system, adaptive beam- forming, fast RLS adaptive equalizer, ${\partial}/4$ QPSK (Quadrilateral Phase Shift Keying) modulator/demodulator, and convolution coding/ Viterbi. Decoding.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.2
• /
• pp.85-94
• /
• 2005

It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.

• KEPCO Journal on Electric Power and Energy
• /
• v.3 no.2
• /
• pp.89-97
• /
• 2017

The substation is a critical node in the power network where power is transformed in the power generation, transmission and distribution system. The IEC 61850 is a global standard which proposes efficient substation automation by defining interoperable communication and data modelling techniques. In order to achieve this level of interoperability and automation, the IEC 61850 (Part 6) defines System Configuration description Language (SCL). The SCL is an XML based file format for defining the abstract model of primary and secondary substation equipment, communications systems and also the relationship between them. It enables the interoperable exchange of data during substation engineering by standardizing the description of applications at different stages of the engineering process. To achieve the seamless interoperability, multi-vendor devices are required to adhere completely to the IEC 61850. This paper proposes an efficient algorithm required for verifying the interoperability of multi-vendor devices by checking the adherence of the SCL file to specifications of the standard. Our proposed SCL validation algorithm consists of schema validation and other functionalities including information model validation using UML data model, the Vendor Defined Extension model validation, the User Defined Rule validation and the IED Engineering Table (IET) consistency validation. It also integrates the standard UCAIUG (Utility Communication Architecture International Users Group) Procedure validation for quality assurance testing. Our proposed algorithm is not only flexible and efficient in terms of ensuring interoperable functionality of tested devices, it is also convenient for use by system integrators and test engineers.