임베디드 시스템 설계에서 효율적인 메모리 접근을 고려한 변수 저장 방법

Storage Assignment for Variables Considering Efficient Memory Access in Embedded System Design

  • 최윤서 (한국과학기술원 전자전산학과) ;
  • 김태환 (서울대학교 전기컴퓨터공학부)
  • 발행 : 2005.02.01

초록

DRAM에 의해 지원되는 페이지(page) 접근 모드나 버스트(burst) 접근 모드를 신중하게 이용하면 DRAM의 접근 시간(access latency) 및 접근 시에 소모되는 에너지를 줄일 수 있음이 많은 설계들에서 입증되었다. 최근에는 변수들을 메모리에 적절하게 배열함으로써 페이지 접근 횟수와 버스트 접근 회수론 각각 극대화시킬 수 있음이 밝혀졌다. 그러나 이러한 최적화문제는 쉽게 최적의 해를 구할 수 없다고 알려졌기 때문에. 주로 간단한 greedy 휴리스틱을 이용해서 풀려졌다. 본 논문은 기존의 방법보다 더 좋은 결과를 얻기 위해서 0-1 선형 프로그래밍(ILP)을 근간으로 한 기법을 제안한다. 벤치마크 프로그램들을 이용한 실험 결과를 보면, 제안된 알고리즘은 각각 OFU(order of first use) 방식과, [2]의 방식, [3]의 방식에 비해 평균적으로 각각 32.3%, 15.1%, 3.5%만큼 페이지 접근 회수론 증가시켰으며, 또한 각각84.4%, 113.5%, 10.1%만큼의 버스트 접근 회수를 증가시켰다.

It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.

키워드

참고문헌

  1. P. R. Panda, N. D. Dutt and A. Nicolau, 'Exploiting Off-Chip Memory Access Modes in High-Level Synthesis,' International Conference on Computer Aided Design, pp. 333-340, 1997 https://doi.org/10.1109/ICCAD.1997.643539
  2. P. R. Panda, N. D. Dutt and A. Nicolau, 'Memory Data Organization for Improved Cache Performance in Embedded Processor Applications,' ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No.4, pp. 384-409, 1997 https://doi.org/10.1145/268424.268464
  3. Y. Choi, and Taewhan Kim, 'Memory Layout Technology for Variables utilizing Efficient DRAM Access Modes in Embedded Systems Design,' Design Automation Conference, pp. 881-886, 2003 https://doi.org/10.1145/775832.776053
  4. N. D. Dutt, 'Memory Organization and Exploration for Embedded Systems-on-Silicon,' International Conference on VLSI and CAD, 1997
  5. IBM, 'IBM Cu -11 Embedded DRAM Macro,' http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/4CBB96F927E2D6D287256B98004EID98/$file/Cu11_embedded_DRAM.10.pdf, 2002
  6. Fujitsu, 'CS70DL Embedded DRAM,' http://www.fme.fujitsu.com/products/asic/pdf/CS70DLFS.pdf, 1999
  7. A. Khare, P. R. Panda, N. D. Dutt and A. Nicolau, 'High-Level Synthesis with Synchronous and RAMBUS DRAMs,' Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 1998
  8. P. Grun, P. Grun, N. D. Dutt and A. Nicolau, 'Memory A ware Compilation Through Accurate Timing Extraction,' Design Automation Conference, pp. 316-321, 2000 https://doi.org/10.1109/DAC.2000.855328
  9. P. Grun, N. Dutt and A. Nicolau, 'APEX: Access Pattern Based Memory Architecture Exploration,' International Symposium on Systems Synthesis (ISSS), pp. 25-32, 2001
  10. K. Ayukawa, T. Watanabe, and S. Narita, 'An Access Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAMs,' IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, pp. 800-806, 1998 https://doi.org/10.1109/4.668996
  11. S. Hettiaratchi, P. Cheung, and T. Clarke, 'Energy Efficient Address Assignment Through Minimized Memory Row Switching,' International Conference on Computer Aided Design, pp. 577-581, 2002 https://doi.org/10.1109/ICCAD.2002.1167590
  12. Laurence A. Wolsey, Integer Programming, Wiley-Interscience, 1998
  13. V. Zivojnovic, J. Velarde, and C. Schlager, 'Dspstone: A DSP-oriented Benchmarking Methodology,' International Conference on Signal Processing Applications and Technology, pp.715-720, 1994
  14. 'Bench mark Archives at CBL,' http://www.cbl.ncsu.edu/CBL_Docs/Bench.html
  15. W. H. Press, et al., Numerical Recipes in C: The Art of Scientific Computing, Cambridge University Press, pp.152,154-155, 1993