Browse > Article

Storage Assignment for Variables Considering Efficient Memory Access in Embedded System Design  

Choi Yoonseo (한국과학기술원 전자전산학과)
Kim Taewhan (서울대학교 전기컴퓨터공학부)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.32, no.2, 2005 , pp. 85-94 More about this Journal
Abstract
It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.
Keywords
Embedded system; DRAM; Code optimization;
Citations & Related Records
연도 인용수 순위
  • Reference
1 W. H. Press, et al., Numerical Recipes in C: The Art of Scientific Computing, Cambridge University Press, pp.152,154-155, 1993
2 Laurence A. Wolsey, Integer Programming, Wiley-Interscience, 1998
3 V. Zivojnovic, J. Velarde, and C. Schlager, 'Dspstone: A DSP-oriented Benchmarking Methodology,' International Conference on Signal Processing Applications and Technology, pp.715-720, 1994
4 'Bench mark Archives at CBL,' http://www.cbl.ncsu.edu/CBL_Docs/Bench.html
5 S. Hettiaratchi, P. Cheung, and T. Clarke, 'Energy Efficient Address Assignment Through Minimized Memory Row Switching,' International Conference on Computer Aided Design, pp. 577-581, 2002   DOI
6 P. Grun, P. Grun, N. D. Dutt and A. Nicolau, 'Memory A ware Compilation Through Accurate Timing Extraction,' Design Automation Conference, pp. 316-321, 2000   DOI
7 Fujitsu, 'CS70DL Embedded DRAM,' http://www.fme.fujitsu.com/products/asic/pdf/CS70DLFS.pdf, 1999
8 P. Grun, N. Dutt and A. Nicolau, 'APEX: Access Pattern Based Memory Architecture Exploration,' International Symposium on Systems Synthesis (ISSS), pp. 25-32, 2001
9 K. Ayukawa, T. Watanabe, and S. Narita, 'An Access Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAMs,' IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, pp. 800-806, 1998   DOI   ScienceOn
10 IBM, 'IBM Cu -11 Embedded DRAM Macro,' http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/4CBB96F927E2D6D287256B98004EID98/$file/Cu11_embedded_DRAM.10.pdf, 2002
11 A. Khare, P. R. Panda, N. D. Dutt and A. Nicolau, 'High-Level Synthesis with Synchronous and RAMBUS DRAMs,' Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 1998
12 P. R. Panda, N. D. Dutt and A. Nicolau, 'Memory Data Organization for Improved Cache Performance in Embedded Processor Applications,' ACM Transactions on Design Automation of Electronic Systems, Vol. 2, No.4, pp. 384-409, 1997   DOI
13 Y. Choi, and Taewhan Kim, 'Memory Layout Technology for Variables utilizing Efficient DRAM Access Modes in Embedded Systems Design,' Design Automation Conference, pp. 881-886, 2003   DOI
14 N. D. Dutt, 'Memory Organization and Exploration for Embedded Systems-on-Silicon,' International Conference on VLSI and CAD, 1997
15 P. R. Panda, N. D. Dutt and A. Nicolau, 'Exploiting Off-Chip Memory Access Modes in High-Level Synthesis,' International Conference on Computer Aided Design, pp. 333-340, 1997   DOI