• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.190-196
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• 2014

This paper proposes a mobile-optimized pedestrian detection method using Cascade of HOG(Histograms of Oriented Gradients) for ADAS(Advanced Driver Assistance System) on smartphones. In order to use the limited resource of mobile platforms efficiently, the method is implemented by the OpenCL(Open Computing Language) library, and its processing time is reduced in the following two aspects. Firstly, the method sets a program build option specifically and adjusts work group sizes as variety of kernels in the host code. Secondly, it utilizes local memory and a LUT(Look-Up Table) in the kernel code to accelerate the program. For performance evaluation, the developed algorithm is compared with the mobile CPU-based OpenCV(Open Computer Vision) for Android function. The experimental results show that the processing speed is 25% faster than the OpenCV hogcascade.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.47-58
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• 1999

As the performance of processors improves, cache memories are used to overcome the difference of speed between processors and main memories. Generally cache memories are embedded and small sizes, fault coverage is a more important factor than test time in testing point of view. A new test algorithm and a new BIST architecture are developed to detect various fault models with a relatively small overhead. The new concurrent BIST architecture uses the comparator of cache management blocks as response analyzers for tag memories. A modified scan-chain is used for pre-testing of comparators which can reduce test clock cycles. In addition several boundary scan instructions are provided to control the internal test circuitries. The results show that the new algorithm can detect SAFs, AFs, TFs linked with CFs, CFins, CFids, SCFs, CFdyns and DRFs models with O(12N), where N is the memory size and the new BIST architecture has lower overhead than traditional architecture by about 11%.

• Interaction and multiscale mechanics
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• v.2 no.4
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• pp.397-411
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• 2009

The effect of soil-structure interaction on a simple single storeyed and two bay space frame resting on a pile group embedded in the cohesive soil (clay) with flexible cap is examined in this paper. For this purpose, a more rational approach is resorted to using the three dimensional finite element analysis with realistic assumptions. The members of the superstructure and substructure are descretized using 20 node isoparametric continuum elements while the interface between the soil and pile is modeled using 16 node isoparametric interface elements. Owing to viability in terms of computational resources and memory requirement, the approach of uncoupled analysis is generally preferred to coupled analysis of the system. However, an interactive analysis of the system is presented in this paper where the building frame and pile foundation are considered as a single compatible unit. This study is focused on the interaction between the pile cap and underlying soil. In the parametric study conducted using the coupled analysis, the effect of pile spacing in a pile group and configuration of the pile group is evaluated on the response of superstructure. The responses of the superstructure considered include the displacement at top of the frame and moments in the superstructure columns. The effect of soil-structure interaction is found to be quite significant for the type of foundation used in the study. The percentage variation in the values of displacement obtained using the coupled and uncoupled analysis is found in the range of 4-17 and that for the moment in the range of 3-10. A reasonable agreement is observed in the results obtained using either approach.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of KIISE:Software and Applications
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• v.27 no.7
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• pp.759-768
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• 2000

The ZG-machine is a space-efficient G-machine, which exploits a simple encoding method, called tag-forwarding, to compress the heap structure of graphs. Experiments on the ZG-machine without garbage collection shows that the ZG-machine saves 30% of heap space and the run-time overhead is no more than 6% than the G-machine. This paper presents the results of further experiments on the ZG-machine with the garbage collector. As a result, the heap-residency of the ZG-machine decreases by 34% on average although the run-time increases by 34% compared to the G-machine. The high rate of the run-time overhead of the ZG-machine is incurred by the garbage collector. However, when the heap size is 7 times the heap-residency, the run-time overhead of the ZG-machine is no more than 12% compared to the G-machine. With the aspect of reduced heap-residency, the ZG-machine may be useful in memory-restricted environments such as embedded systems. Also, with the development of a more efficient garbage collector, the run-time is expected to decrease significantly.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2344-2346
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• 2002

A vacuum control system has been developed for using Ethernet Multi Serial Device Severs (EMSDS) for the Pohang Accelerator Laboratory (PAL) storage ring. There are 124 vacuum ion pumps at the storage ring. It was a very important problem to solve the problem how to control such a big number of vacuum pumps distributed around the ring. After discussions, we decided to develop a serial to ethernet interrace device sever that will be mounted in the control system rack. It has a 32-bits microprocessor embedded Linux, 12 ports RS485 (or RS232) slave interface. one channel 10/100BaseTx ethernet host port, one channel UART host port, and 16 Mbytes large memory buffer. These vacuum pumps are connected to Ion-Pump serial controllers, which chop the AC current so as to control the current in the pumps. The EMSDS connect either 100BaseTx or 10BaseT ethernet networks to asynchronous serial ports for communication with serial device. It can simultaneously control up to 12 ion-pump serial controllers. 12 EMSDS are connected to a personal computer (PC) through the network. The PC can automatically control the EMSDS by sending a set of commands through the TCP/IP network. Upon receiving a command from a PC running under Windows2000 through the network, the EMSDS communicate through the stave serial interrace ports to ion-pump controller. We added some software components on the top of EPICS (Experimental Physics and Industrial Control System) toolkit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03a
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• pp.21-21
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• 2010

(Ba,Sr)$TiO_3$ (BST) thin film with a perovskite structure has potential for the practical application in various functional devices such as nonvolatile-memory components, capacitor, gate insulator of thin-film transistors, and electro-optic devices for display. Normally, the BST thin films derived from sol-gel and sputtering are amorphous or partially crystalline when processed below $600^{\circ}C$. For the purpose of integrating BST thin film directly into a Si-based read-out integrated circuit (ROIC), it is necessary to process the BST film below $400^{\circ}C$. The microstructural and electrical properties of low-temperature crystallized BST film were studied. The BST thin films have been fabricated at $350^{\circ}C$ by UV-assisted rapidly thermal annealing (RTA). The BST films are in a single perovskite phase and have well-defined electrical properties such as high dielectric constant, low dielectric loss, low leakage current density, and high breakdown voltage. Photoexcitation of the organics contained in the sol-gel-derived films by high-intensity UV irradiation facilitates elimination of the organics and formation of the single-crystalline phase films at low temperatures. The amorphous BST thin film was transformed to a highly (h00)-oriented perovskite structure by high oxygen pressure processing (HOPP) at as low as $350^{\circ}C$. The dielectric properties of BST film were comparable to (or even better than) those of the conventionally processed BST films prepared by sputtering or post-annealing at temperature above $600^{\circ}C$. When external pressure was applied to the well-known contractive BST system during annealing, the nucleation energy barrier was reduced; correspondingly, the crystallization temperature decreased. The UV-assisted RTA and HOPP, as compatible with existing MOS technology, let the BST films be integrated into radio-frequency circuit and mixed-signal integrated circuit below the critical temperature of $400^{\circ}C$.