한국항행학회논문지 (Journal of Advanced Navigation Technology)

  • 제18권6호
  • /
  • Pages.600-608
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  • 2014
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  • 1226-9026(pISSN)
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  • 2288-842X(eISSN)
한국항행학회 (The Korean Navigation Institute)
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H/W-S/W 병행설계를 이용한 CABAC의 효율적인 하드웨어 구현

An Efficient Hardware Implementation of CABAC Using H/W-S/W Co-design

  • 조영주 (광운대학교 전자통신공학과) ;
  • 고형화 (광운대학교 전자통신공학과)
  • Cho, Young-Ju (Department of Electronics and Communication Engineering, KwangWoon University) ;
  • Ko, Hyung-Hwa (Department of Electronics and Communication Engineering, KwangWoon University)
  • 투고 : 2014.11.28
  • 심사 : 2014.12.24
  • 발행 : 2014.12.30
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초록

본 논문에서는 CABAC (context adaptive binary arithmetic coding)를 하드웨어로 구현하기 위하여 병행설계 (co-design) 기법을 사용하였다. H.264/AVC의 부호기 전체를 C언어로 개발하고, CABAC만을 하드웨어 IP로 설계하고, H.264/AVC의 나머지 부분은 소프트웨어로 설계하였다. CABAC의 문맥모델러 부분을 하드웨어로 설계하여 연산값을 지속적으로 업데이트시킴으로써 메모리를 효율적으로 사용하고 스트림을 절감시키는 설계를 하였다. 설계된 IP는 Xilinx ML410 보드의 Virtex-4 FX60 FPGA에 다운로드하여 MicroBlaze CPU를 이용하여 H.264/AVC의 참조 소프트웨어인 JM과 연동하도록 설계하였다. 기능 시뮬레이션은 ModelSim을 이용하였다. 기존의 CABAC 하드웨어 모듈이 레지스터 레벨에서 설계하여 개발기간이 오래 걸리는데 비하여 본 논문의 설계 기법은 소프트웨어 엔지니어가 쉽게 하드웨어를 개발하는 것이 가능해지는 장점이 있으며 설계시간도 짧다. 또한, 동일한 방법으로 구현된 CAVLC 모듈과 Slice 사용량을 비교해볼 때, 1/3 이하로 감축됨을 보였다. 본 연구에서 제시한 개발 방법은 임베디드 환경에서 고성능 동영상 압축 부호화시 하드웨어 가속기가 필요한 부분을 설계할 때 유용할 것으로 보인다.

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

키워드

참고문헌

  1. B. Bross, High efficiency video coding text specification draft 10, JCT-VC of ISO/IEC and ITU-T, Geneva, Jan. 2003.
  2. JVT G050r1, Draft ITU-T recommendation and final draft international standard of joint video specification, ITU-T, 14496-10, May. 2003.
  3. D. G. Sim, Next generation video coding standard technique, IC Design Education Center Newsletter, pp. 04-09, July 2011.
  4. D. Marpe, H. Schwarz, and T. Wiegand, "Context-based adptive arithmetic coding in the H.264/AVC video compression standard," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 620-636, July 2003. https://doi.org/10.1109/TCSVT.2003.815173
  5. D. Marpe and T. Wiegand, "A highly efficient multiplication-free binary arithmetic coder, and its application in video coding," in Proceedings IEEE International Conference on Image Processing 2003, Barcelona: Spain, Sept. 2003.
  6. X. H.Tian, T. M.Le, X. Jiang, and Y. Lian, "A HW encoder with efficient context access scheme for H.264/AVC," IEEE International Symposium in Circuits and Systems, pp. 18-21, May 2008.
  7. F. Zargari and E. Azimi, "An efficient hardware implementation for H.264 binary arithmetic encoder," in Proceedings of the 14th International Computer Society of Iran Computer Conference, Tehran: Iran, pp. 105-109, 2009.
  8. K. Andra, T. Acharya, and C. Chakrabarti, "A multi-bit binary arithmetic coding technique," in 2000 International on Image Processing, Vancouver: Canada, pp. 928-931, Sept. 2000.
  9. W. B. Pennebaker, J. J.Mitchell, G. G. Langdon and R. B. Arps, "An overview of the basic principles of the q coder adaptive binary arithmetic coder," IBM Journal of Research and Envelopment, No. 6, pp. 717-726, Nov. 1988.
  10. X. Tian, Entropy Coders of the H.264/AVC Standard, Berlin Heidelberg, Germay: Springer-Verlag, 2011.
  11. C. Shinya, H.264/AVC Textbook, Seoul, Korea: Hongrung Publishing Company, 2005.
  12. Fraunhofer Heinrich-Hertz-Institut[Internet]. Available: http://www.hhi.fraunhofer.de/de/kompetenzfelder/image-processing/research-groups/image-video-coding/statistical -modeling-codi ng/fast-adapti ve-binary-arithmetic-coding-m-coder.html
  13. P. S. Liu, J. W. Chen and Y.L. Lin, "A hardwired context-based adaptive binary arithmetic encoder for H.264 advanced video coding," IEEE International Symposium on VLSI Design, Vol. 1, pp. 1-4, Apr. 2007.
  14. Impulse Point and Sate Connect Manages BYOD[Internet]. Available: http://www.impulse.com
  15. D. Pellerin and S. Thibault, Practical FPGA programming in C, New Jersey, United States: Prentice Hall, 2005.
  16. D. S. Wang, Hardware implementation of DCT and CAVLC for H.264/AVC based on co-design, M.S. thesis, Kwangwoon University, Seoul, Dec. 2010.
  17. R. R. Osorio and J. D. Bruguera, "A new architecture for fast arithmetic coding in H.264 advanced video coder," in 8th Euromicro Conference on Digital System Design, Porto: Portugal, pp. 298-305, Sept. 2005.
  18. J. L. Nunez-Yanez, V. A. Chouliaras, D. Alfonso, and F.S.Rovati, "Hardware assisted rate distortion optimization with embedded cabac accelerator for the H.264 advanced video codec," IEEE Transactions on Consumer Electronics, Vol. 52, No. 2, pp. 590-597, 2006. https://doi.org/10.1109/TCE.2006.1649684