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http://dx.doi.org/10.12673/jant.2014.18.6.600

An Efficient Hardware Implementation of CABAC Using H/W-S/W Co-design  

Cho, Young-Ju (Department of Electronics and Communication Engineering, KwangWoon University)
Ko, Hyung-Hwa (Department of Electronics and Communication Engineering, KwangWoon University)
Publication Information
Journal of Advanced Navigation Technology / v.18, no.6, 2014 , pp. 600-608 More about this Journal
Abstract
In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.
Keywords
High efficiency video coding; Context adaptive binary arithmetic coding; H.264; M-coder;
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