• Journal of the Korean Society for Precision Engineering
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• v.20 no.2
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• pp.94-103
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• 2003

In case of environment requiring safety such as human body and requiring flexible shape, a conventional mechanical actuator system does not satisfy requirements. Therefore, in order to solve these problems. a research of various smart material such as EAP (Electro Active Polymer), EAC (Electro Active Ceramic) and SMA (Shape Memory Alloy) is in progress. Recently, the highest preferring material among various smart material is EP (Electrostictive Polymer), because it has very fast response time, powerful force and large displacement. The previous researches have been studied properties of polymer and simple control, but present researches are studied a polymer actuator. An EP (Electostrictive Polymer) actuator has properties which change variably ils shape and environmental condition. Therefore, in order to coincide with a user's purpose, it is important not only to decide a shape of actuator and mechanical design but also to investigate a efficient controller. In this paper, we constructed the control logic with an adaptive fuzzy algorithm which depends on the physical properties of EP that has a dielectric constant depending on time. It caused for a sub-actuator to operate at the same time that a sub-actuator system operation increase with a functional improvement and control efficiency improvement in each actuator, hence it becomes very important to manage it effectively and to control the sub-system which Is operated effectively. There is a limitation on the management of Main-host system which has multiple sub-system, hence it brings out the Multi-Vehicle Control process that disperse the task efficiently. Controlling the multi-dispersion system efficiently, it needs the research of Main-host system's scheduling, data interchange between sub-actuators, data interchange between Main-host system and sub-actuator system, and data communication process. Therefore in this papers, we compared the fuzzy controller with the adaptive fuzzy controller. also, we applied the scheduling method for efficient multi-control in EP Actuator and the algorithm with interchanging data, protocol design.

• Journal of the Korea Society of Computer and Information
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• v.17 no.9
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• pp.103-112
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• 2012

Recently, the infrastructure to be connected to the internet is much provided, there is more and more need to connect electric or electronic products to the internet to monitor or control them remotely. However, most of the existing products lack the network interface, so it was very inconvenient to be connected to the internet. Therefore, this article designs and realizes the internet outlet allowing real-time scheduling that can control the power remotely on the internet by using the hardware TCP/IP processor. The realized product consumes low production cost because it can be realized by using the hardware TCP/IP processor and the 8-bit small microprocessor. In addition, the product can be used widely in both wired and wireless environments with a variety of user interface, including the dedicated control program which provides the environment configuration functions; embedded web service that enables the webpage to be saved on the external flash memory; Android smartphone application; motion recognition control environment that uses the OpenCV computer vision library, etc.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.1
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• pp.74-81
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• 2003

In this study, we'd implemented a real time embedded speech recognition system that requires minimum memory size for speech recognition engine and DB. The word to be recognized consist of 40 commands used in a PCS phone and 10 digits. The speech data spoken by 15 male and 15 female speakers was recorded and analyzed by short time analysis method, which window size is 256. The LPC parameters of each frame were computed through Levinson-Burbin algorithm and they were transformed to Cepstrum parameters. Before the analysis, speech data should be processed by pre-emphasis that will remove the DC component in speech and emphasize high frequency band. Baum-Welch reestimation algorithm was used for the training of HMM. In test phone, we could get a recognition rate using likelihood method. We implemented an embedded system by porting the speech recognition engine on ARM core evaluation board. The overall recognition rate of this system was 95%, while the rate on 40 commands was 96% and that 10 digits was 94%.

• Journal of IKEEE
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• v.15 no.4
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• pp.345-353
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• 2011

Recently portable mobile devices such as smart-phones and notebooks have rapidly increasing demands. Those devices consume more power because they are expected to offer more complex functionality including multimedia features. For these reasons engineering efforts are changing to focus on maximizing energy efficiency within a limited battery capacity instead of increasing computational performance. In this paper, we propose a battery management system using event driven programming technique on a embedded processor. We also show that the proposed system satisfies SBS (Smart Battery Specification) v1.1. The proposed system maintains minimum code size and memory size comparing to those of RTOSs. The proposed system can be also easily incorporated in the conventional RTOSs as a form of firmware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.9
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• pp.1180-1186
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• 2020

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• Korean Journal of Materials Research
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• v.20 no.5
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• pp.241-245
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• 2010

One of the weak points of the Cr-doped SZO is that until now, it has only been fabricated on perovskite substrates, whereas NiO-ReRAM devices have already been deposited on Si substrates. The fabrication of RAM devices on Si substrates is important for commercialization because conventional electronics are based mainly on silicon materials. Cr-doped ReRAM will find a wide range of applications in embedded systems or conventional memory device manufacturing processes if it can be fabricated on Si substrates. For application of the commercial memory device, Cr-doped $SrZrO_3$ perovskite thin films were deposited on a $SrRuO_3$ bottom electrode/Si(100)substrate using pulsed laser deposition. XRD peaks corresponding to the (112), (004) and (132) planes of both the SZO and SRO were observed with the highest intensity along the (112) direction. The positions of the SZO grains matched those of the SRO grains. A well-controlled interface between the $SrZrO_3$:Cr perovskite and the $SrRuO_3$ bottom electrode were fabricated, so that good resistive switching behavior was observed with an on/off ratio higher than $10^2$. A pulse test showed the switching behavior of the Pt/$SrZrO_3:Cr/SrRuO^3$ device under a pulse of 10 kHz for $10^4$ cycles. The resistive switching memory devices made of the Cr-doped $SrZrO_3$ thin films deposited on Si substrates are expected to be more compatible with conventional Si-based electronics.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.673-677
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• 2010

Recently, NAND flash memory has been widely used in embedded systems, personal computers, and server systems because of its attractive features, such as non-volatility, fast access speed, shock resistance, and low power consumption. Due to its hardware characteristics, specifically its 'erase-before-write' feature, Flash Translation Layer is required for using flash memory like hard disk drive. Many FTL schemes have been proposed, but conventional FTL schemes have problems such as block thrashing and block associativity problem. The KAST scheme tried to solve these problems by limiting the number of associations between data block and log block to K. But it has also block thrashing problem in random access I/O pattern. In this paper, we proposed a new FTL scheme, UDA-LBAST. Like KAST, the proposed scheme also limits the log block association, but does not limit data block association. So we could minimize the cost of merge operations, and reduce merge costs by using a new block reclaim scheme, log block garbage collection.