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Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec

  • Kim, Sunwoong (Inter-university Semiconductor Research Center, Department of Electrical Engineering, Seoul National University) ;
  • Jang, Ji Hun (Department of Information and Communication Engineering, Inha University) ;
  • Lee, Hyuk-Jae (Inter-university Semiconductor Research Center, Department of Electrical Engineering, Seoul National University) ;
  • Rhee, Chae Eun (Department of Information and Communication Engineering, Inha University)
  • Received : 2016.10.31
  • Accepted : 2017.03.27
  • Published : 2017.06.30

Abstract

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

Keywords

References

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