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http://dx.doi.org/10.6109/jkiice.2020.24.9.1180

High Speed and Robust Processor based on Parallelized Error Correcting Code Module  

Kang, Myeong-jin (School of Electronics Engineering, Kyungpook National University)
Park, Daejin (School of Electronics Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.24, no.9, 2020 , pp. 1180-1186 More about this Journal
Abstract
One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.
Keywords
Parallelized ECC block; Accuray improvement; Releasing bottleneck; Embedded system;
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