Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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High Speed and Robust Processor based on Parallelized Error Correcting Code Module

병렬화된 에러 보정 코드 모듈 기반 프로세서 속도 및 신뢰도 향상

  • Kang, Myeong-jin (School of Electronics Engineering, Kyungpook National University) ;
  • Park, Daejin (School of Electronics Engineering, Kyungpook National University)
  • Received : 2020.06.17
  • Accepted : 2020.07.17
  • Published : 2020.09.30
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Abstract

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.

임베디드 시스템 중 하나인 TPU (Tiny Processing Unit)를 사용하는 데에는 많은 제약들이 따른다. 외부 충격에 의해 데이터 통신 중 잡음이 발생하거나, 충분한 전력이 공급되지 않아 문턱전압을 넘지 못해 올바른 값 전달이 이루어지지 않는 경우가 있다. 이러한 문제점들을 해결하기 위해 많은 임베디드 시스템에서는 ECC (Error Correcting Code)를 사용하는데, ECC를 추가하게 되면서 메모리에서 데이터를 읽어오는 시간이 더 오래 걸리게 되는 문제점이 발생한다. 따라서 우리는 ECC 처리된 코드를 읽어오는 과정을 병렬처리하여 병목현상을 완화하고 TPU의 속도 및 데이터 안정성을 높이는 모델을 제안한다. 제안된 구조는 기존 구조에 비해 메모리를 조금 더 사용하여 안정성과 더 빠른 속도를 보여준다. 실험은 행렬의 연산을 사용하여 진행되었으며, 제안된 구조는 이전의 구조보다 7% 빠른 속도를 보여준다.

Keywords

References

  1. S. Saha, S. Ehsan, A. Stoica, R. Stolkin and K. McDonald-Maier, "Real-Time Application Processing for FPGA-Based Resilient Embedded Systems in Harsh Environments," 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, pp. 299-304, 2018.
  2. J. Chen and M. Shafique, "Embedded software reliability for unreliable hardware," 2014 International Conference on Embedded Software (EMSOFT), Jaypee Greens, pp. 1-1, 2014.
  3. D. Lee, M. Kang, P. Plesznik, J. Cho and D. Park, "Scrambling Technique of Instruction Power Consumption for Side-Channel Attack Protection," 2020 International Conference on Electronics, Information, and Communication (ICEIC), Barcelona, Spain, pp. 1-2, 2020.
  4. G. Subhasri, and N. Radha, "VLSI design of Parity check Code with Hamming Code for Error Detection and Correction," 2019 International Conference on Intelligent Computing and Control Systems (ICCS), Madurai, India, pp. 15-20, 2019. doi: 10.1109/ICCS45141.2019.9065790.
  5. J. Edwards and S. O'Keefe, "Eager recirculating memory to alleviate the von Neumann Bottleneck," 2016 IEEE Symposium Series on Computational Intelligence (SSCI), Athens, pp. 1-5, 2016.
  6. M. Ramakrishnan and J. Harirajkumar, "Design of 8T ROM embedded SRAM using double wordline for low power high speed application," 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, pp. 0921-0925, 2016.
  7. M. Sever and E. Cavus, "Parallelizing LDPC Decoding Using OpenMP on Multicore Digital Signal Processors," 2016 45th International Conference on Parallel Processing Workshops (ICPPW), Philadelphia, PA, pp. 46-51, 2016.
  8. D. Park and T. G. Kim, "Safe microcontrollers with error protection encoder-decoder using bit-inversion techniques for on-chip flash integrity verification," 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE), Tokyo, pp. 299-300, 2013.
  9. L. Azriel, A. Mendelson and U. Weiser, "Peripheral memory: a technique for fighting memory bandwidth bottleneck," in IEEE Computer Architecture Letters, vol. 14, no. 1, pp. 54-57, Jan.-Jun. 2015. https://doi.org/10.1109/LCA.2014.2319077
  10. J. Kim, J. Cho and D. Park, "Low-Power Command Protection Using SHA-CRC Inversion-Based Scrambling Technique for CAN-Integrated Automotive Controllers," 2018 IEEE Conference on Dependable and Secure Computing (DSC), Kaohsiung, Taiwan, pp. 1-2, 2018.
  11. A. Kafi, A. Rahman, B. Mahjabeen and M. Rahman, "An efficient design of FSM based 32-bit unsigned high-speed pipelined multiplier using Verilog HDL," 8th International Conference on Electrical and Computer Engineering, Dhaka, pp. 164-167, 2014.