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http://dx.doi.org/10.5392/JKCA.2010.10.3.064

Design of an Asynchronous Instruction Cache based on a Mixed Delay Model  

Jeon, Kwang-Bae (충북대학교 정보통신 공학과)
Kim, Seok-Man (충북대학교 정보통신 공학과)
Lee, Je-Hoon (강원대학교 전자공학과)
Oh, Myeong-Hoon (한국전자통신연구원)
Cho, Kyoung-Rok (충북대학교 정보통신 공학과)
Publication Information
The Journal of the Korea Contents Association / v.10, no.3, 2010 , pp. 64-71 More about this Journal
Abstract
Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.
Keywords
Completion Signal; Cache Memory; Delay-Insensitive; CAM;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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