• IEMEK Journal of Embedded Systems and Applications
• /
• v.9 no.4
• /
• pp.211-217
• /
• 2014

Cyber-Physical Systems(CPS) that mostly provides safety-critical and mission-critical services requires high reliability, so that system testing is an essential and important process. Hardware-In-the-Loop Simulation(HILS) is one of the extensively used techniques for testing hardware systems. However, most conventional HILS has problems that it is difficult to support a distributed operating environment and to reuse a HILS platform. In this paper, we introduce EcoHILS(ETRI CPS Open Human-Interactive hardware-in-the-Loop Simulator) in order to test CPS effectively. Moreover, feasibility tests and performance tests of EcoHILS are performed to confirm its effectiveness.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.6 no.4
• /
• pp.243-248
• /
• 2011

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

• Journal of Korea Multimedia Society
• /
• v.17 no.3
• /
• pp.324-332
• /
• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• ETRI Journal
• /
• v.31 no.3
• /
• pp.339-341
• /
• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.258-260
• /
• 2006

In this paper, we designed a embedded system that will perform a primary role of Tangible Space implementation. This hardware includes function of image capture through camera interface, image process and sending off image information by LAN (local area network) or WLAN(wireless local area network). We define this hardware as a network based Visual Agent Platform for Tangible Space

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.5
• /
• pp.350-354
• /
• 2009

To optimize the performance of software programs, it is important to know certain hardware parameters such as the CPU speed, the cache size, the number of TLB entries, and the parameters of the memory subsystem. There exist several ways to obtain the values of various hardware parameters. Firstly. the values can be taken from the hardware manual. Secondly, the parameters can be obtained by calling functions provided by the operating systems. Finally, hardware detection programs can find the desired values. Such programs are usually executed on PC or server systems and report the CPU speed, the cache size, the number of TLB entries, and so on. However, they do not sufficiently detect the parameters of one of the most important parts of the computer concerning performance, namely the memory bank layout in the memory subsystem. In this paper, we present an algorithm to detect the memory bank parameters. We run an implementation of our algorithm on various embedded systems and compare the detected values with the real hardware parameters. The results show that the presented algorithm detects the cache size, the number of TLB entries, and the memory bank layout with high accuracy.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.6
• /
• pp.477-487
• /
• 2005

As embedded system grows in size and complexity, the importance of the technique for dynamic memory allocation has increased. The objective of this paper is to measure the performance of dynamic memory allocation by varying both hardware and software design parameters for embedded systems. Unlike torrent performance evaluation studies that have presumed the single threaded system with single address spate without OS support, our study adopts realistic environment where the embedded system runs on Linux OS. This paper contains the experimental performance analyses of dynamic memory allocation method by investigating the effects of each software layer and some hardware design parameters. Our quantitative results tan be used to help system designers design high performance, low power embedded systems.

• Journal of Korea Multimedia Society
• /
• v.18 no.6
• /
• pp.723-733
• /
• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• Journal of KIISE:Software and Applications
• /
• v.33 no.11
• /
• pp.915-922
• /
• 2006

Recently, the requirements of the embedded software are getting diverse as the diversity of embedded software application fields increases. The systematic development methods are issued to deal with the dependency between hardware and software. However, the existing development methods have not considered the software's close connection to hardware and the high-level reusability for common requirements of several similar domains. In this paper, we propose a design method of development process model of product lines to support an efficient development method for embedded software. For this, we firstly suggest a domain scoping method and an IDEF0(Integration DEFinition)-based business model for extracting the efficient requirements. Next, we present a component deriving method based on the service architecture and an architecture design method after considering the hardware dependency. And we explain the artifacts of MSDFS(Multi Sensor Data Fusion System) at each design step in order to show how the proposed model can be applied to the embedded software development.

• Journal of KIISE:Software and Applications
• /
• v.37 no.4
• /
• pp.323-339
• /
• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.