• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1713-1717
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• 2008

We have developed a nanoparticle focusing mask which can generate particle arrays directly on the large area with high resolution. Using this mask, nanomaterials are precisely deposited onto desired positions on a substrate surface. We obtained various sizes of arrays ranging from 80 nm to 6 ${\mu}m$ with silver and copper nanoparticles that are generated by a spark discharge and an evaporation-condensation method. The feather size is much smaller than that of mask openings due to the focusing effects, like electrostatic lens, caused by charge or electric potential on insulator mask surface, which also prevent a mask clogging. The particle array size depends on the size of mask open patterns and focusing effects near the mask relate to ion flow rate and electric potential. We have demonstrated that diverse size of arrays with high resolution could be obtained repeatedly using the same sized mask in atmosphere.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1482-1483
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• 2006

고전압 방전시험 장치는 국제전기기술위원회 규격(IEC 61000-4-2)에서 규정하고 있는 콘덴서 방식을 사용하며, 매우 짧은 시간에 방전함으로서 펄스 형태의 방전전류가 통전된다. 이러한 정전기적인 방전에 의해 전자기기에 고장을 발생시키며 이를 검증하는 방법으로 정전기 내성시험법이 있다. 본 논문에서는 첫째로 방전장치가 발생하는 잡음 전계량을 측정하였고, 둘째로 방전장치를 시험시료에 근접하는 방법에 따른 시험시료에 미치는 영향을 실험을 통해 검증하였고, 셋째로 근접방법에 따른 정전유도 현상이 시험시료에 미치는 영향을 실험적으로 검증하였다. 이러한 세 가지 현상을 바탕으로 시험시료가 고전압 방전장치를 근접 방전하여 방전을 유발시켰을 때의 전자파의 영향에 내성을 갖고 있는지를 검증하는 새로운 시험방법을 제안하였다.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.495-502
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• 2014

Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.1-7
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• 2014

A bidirectional transient voltage suppression (TVS) diode consisting of specially designed $p^--n^{{+}+}-p^-$ multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped $n^{{+}+}$ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as $0.2{\Omega}$, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ${\pm}4.0$ kV of MM and ${\pm}14$ kV of IEC, and exceeding ${\pm}8$ kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in $p^--n^{{+}+}-p^-$ multi-junctions.

• Journal of the Korean Institute of Gas
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• v.15 no.3
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• pp.6-10
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• 2011

Experimental studies were carried out to investigate the effects on flame propagation of gasoline-air mixtures by different electrostatic discharge energies in a cylindrical chamber. Three different ignition energies were used: 1 mJ, 50 mJ and 98 mJ. In this work, a high-speed particle image velocimetry technique was applied to visualize the flow-field around ignition electrodes. It was found that as the ignition energy increased, the ignition kernel was different. The different ignition kernel caused different flame initiation. During the flame initiation, the higher ignition energy was applied, the higher flame speed was observed. However, with increasing time, the flame speeds were independent of the ignition energies used. Theses observed flame behaviors were similar to computational simulations shown in the literature. It was also found that as the ignition energies increased, the velocities of unburnt mixtures ahead of propagating flame fronts increased.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.35-40
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• 2008

High performance light emitting diodes(LEDs) have been developed using GaN-based materials grown on sapphire substrates in recent years. Although these LEDs are already commercially available, we have to consider electrostatic discharge(ESD) damage related to both basic materials of diode and miniaturization of LEDs. ESD damage is one of the important parameters influencing reliability of the light emitting devices. We investigated mass production of GaN-based LEDs suffered from ESD during production process and present the solutions in order to improve the ESD problem. Most of EDS problems were controlled by using instruments properly and improvement of the process circumstances as well.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.4
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• pp.524-533
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• 2003

DBD(Dielectric Barrier Discharge) plasma in air is well established for the production of large quantities of ozone and is more recently being applied to aftertreatment processes for HAPs(Hazardous Air Pollutants). Aim of this work is to determine design and operating parameters of a hybrid air cleaning system. DBD and ESP(Electrostatic Precipitator) are used as nano particle charger and collector, respectively. Pelletized MnO$_2$ catalyst or activated carbon is used fer ozone decomposition or adsorption material. AC voltage of 7～10 KV(rms) and 60 Hz is used as DBD plasma source. DC - 8 KV is applied to the ESP for particle collection. The overall particle collection efficiency for the hybrid system is over 85 % under 0.64 m/s face velocity. Ozone decomposition efficiency with pelletized MnO$_2$ catalyst or activated carbon packed bed is over 90 % when the face velocity is under 0.4 m/s in dry air.