• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.415-420
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• 2007

Generally, a diode package consists of the synthetic resin that has good durability but low thermal conductivity. The surface mounted type fast recovery diode was fabricated by using ceramic package. Its main manufacture processes are composed of soldering, sillicon coating and side termination. And it has various advantages that diode is small, easy manufacture and fast cooling. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5.28 ns, 1322 V, 1.08 V, $0.45\;{\mu}A$, respectively.

• 한국전기전자재료학회논문지
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• 제29권2호
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• pp.75-78
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• 2016

This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained $60{\mu}m$ N-drift layer depth, 791.29 V breakdown voltage, $0.248{\Omega}{\cdot}cm^2$ on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package.

• 한국산업융합학회 논문집
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• 제2권2호
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• E2M - 전기 전자와 첨단 소재
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• 제10권6호
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• E2M - 전기 전자와 첨단 소재
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• 제16권7호
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• pp.14-20
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• 2003

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.25.1-25.1
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• 2011

Over the past few decades, metallic nanoparticles (NPs) have been of great interest due to their unique mesoscopic properties which distinguish them from those of bulk metals; such as lowered melting points, greater versatility that allows for more ease of processability, and tunable optical and mechanical properties. Due to these unique properties, potential opportunities are seen for applications that incorporate nanomaterials into optical and electronic devices. Specifically, the development of metallic NPs has gained significant interest within the electronics field and technological community as a whole. In this study, gold (Au) pads for surface finish in electronic package were developed by inkjet printing of Au NPs. The microstructures of inkjet-printed Au film were investigated by various thermal treatment conditions. The film showed the grain growth as well as bonding between NPs. The film became denser with pore elimination when NPs were sintered under gas flows of $N_2$-bubbled through formic acid ($FA/N_2$) and $N_2$, which resulted in improvement of electrical conductance. The resistivity of film was 4.79 ${\mu}{\Omega}$-cm, about twice of bulk value. From organic anlayses of FTIR, Raman spectroscopy, and TGA, the amount of organic residue in the film was 0.43% which meant considerable removal of the solvent or organic capping molecules. The solder ball shear test was adopted for solderability and shear strength value was 820 gf (1 gf=9.81 mN) on average. This shear strength is good enough to substitute the inkjet-printed Au nanoparticulate film for electroplating in electronic package.

• Journal of Mechanical Science and Technology
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• 제18권3호
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• pp.357-369
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• 2004

The purposes of the paper are to analyze the fracture phenomenon by delamination and cracking when the encapsulant of plastic IC package with polyimide coating shows viscoelastic behavior under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by the approaches of stress analysis and fracture mechanics. The model is the plastic SOJ package with the polyimide coating surrounding chip and dimpled diepad. On the package without cracks, the optimum position and thickness of polyimide coating to decrease the maximum differences of strains at the bonding surfaces of parts of the package are studied. For the model delaminated fully between the chip and the dimpled diepad, C(t)-integral values are calculated for the various design variables. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.96-99
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• 2000

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.